Tiled display

• US 7,394,194 B2
• Filed: 11/23/2004
• Issued: 07/01/2008
• Est. Priority Date: 11/23/2004
• Status: Active Grant

• Current Assignee: Global OLED Technology LLC (LG Display Co., Ltd.)
• Original Assignee: Eastman Kodak Company
• Inventors: Cok, Ronald S.
• Primary Examiner(s): Roy; Sikha
• Application Number:
  US10/995,585
• Publication Number:
  US 20060108913A1
• Time in Patent Office: 1,316 Days
• Field of Search: None
• US Class Current: 313/506
• CPC Class Codes: H10K 59/18 Tiled displays
• CPC Class Codes: Y10S 428/917 Electroluminescent

Abstract

A tiled display structure having a plurality of display tiles. Each display tile comprising a tile substrate, first electrodes located on a first side of the tile substrate, light emitting or controlling materials deposited over the first electrodes, and second electrodes deposited over the light emitting or controlling material. A back panel is provided having a plurality of back-panel conductors located on a first side of the back panel. The display tiles are mounted upon the back panel with the first side of the tile substrate adjacent to the first side of the back panel and the first and second electrodes electrically connected from the first side of the tile substrate through electrical standoff connectors to the back-panel conductors.

Claims

1. A tiled display structure, comprising:

a) a plurality of display tiles, each display tile comprising a tile substrate, first electrodes located on a first side of the tile substrate, light emitting or controlling materials deposited over a portion of the first electrodes leaving a first contact area without any light-emitting material or light-controlling material deposited thereon, and second electrodes being directly deposited over the light emitting or controlling material and connected directly onto the first side of the tile substrate in a second contact area different from the first contact area;

b) a back panel having a plurality of back-panel conductors located on a first side of the back panel; and

c) wherein the display tiles are mounted upon the back panel with the first side of the tile substrate adjacent to the first side of the back panel and the first and second electrodes electrically connected from the first and second contact areas on the first side of the tile substrate through electrical standoff connectors to the back-panel conductors.

2. The tiled display claimed in claim 1 wherein the display tiles are passive-matrix displays.

3. The tiled display claimed in claim 1 wherein the display tiles are active-matrix displays.

4. The tiled display claimed in claim 1 wherein the display tiles emit light through the tile substrate.

5. The tiled display claimed in claim 1 wherein the first electrodes are connected through a thin-film circuit to the electrical standoff connectors.

6. The tiled display claimed in claim 1 wherein the display tiles form a two-dimensional array on the back panel.

7. The tiled display claimed in claim 1 wherein the display tiles form a one-dimensional array on the back panel.

8. The tiled display claimed in claim 1 wherein the standoff connectors are formed from solder, pins, or deformable metal structures.

9. The tiled display claimed in claim 1 wherein the light emitting materials is an OLED material.

10. The tiled display claimed in claim 9 wherein the light emitting material further comprise layers of materials including one or more layers of hole-injection material, hole-transport material, emissive material, electron-injection material, and electron-transport material.

11. The tiled display claimed in claim 1 wherein the tile substrates have edges that are glued together with an adhesive optically matched to the tile substrate.

12. The tiled display claimed in claim 11 wherein the adhered edges form a hermetic seal.

13. The tiled display claimed in claim 11 wherein the glue has an optical index matched to the optical index of the tile substrate.

14. The tiled display claimed in claim 1 further comprising an optical coating located on a second side of the tile substrate.

15. The tiled display claimed in claim 1 further comprising an encapsulating cover located over the second side of the tile substrate and affixed to the back panel.

16. The tiled display claimed in claim 1 wherein the encapsulating cover is a layer.

17. The tiled display claimed in claim 1 further comprising an encapsulating material located between the first side of the tile substrate and the first side of the back panel.

18. The tiled display claimed in claim 1 wherein the electrical standoff connections are located on the periphery of the tile substrate.

19. The tiled display claimed in claim 1 wherein the electrical standoff connections are located between the first electrodes.

20. The tiled display claimed in claim 1 further comprising a display area and wherein the electrical standoff connections are located within the display area.

21. The tiled display claimed in claim 1 further comprising an electrically insulating and thermally conductive material located between the back panel and the display tile.

22. The tiled display claimed in claim 1 further sealing materials located between each display tile and the back panel to seal each display tile with the back panel.