Current-mode control for switched step up-step down regulators

• US 7,394,231 B2
• Filed: 02/08/2005
• Issued: 07/01/2008
• Est. Priority Date: 02/08/2005
• Status: Active Grant

• Current Assignee: Analog Devices International Unlimited Company (Analog Devices, Inc.)
• Original Assignee: Linear Technology Corporation (Analog Devices, Inc.)
• Inventors: Flatness, Randy G., Zhou, Xunwei
• Primary Examiner(s): Sterrett; Jeffrey L.
• Assistant Examiner(s): BEHM, HARRY RAYMOND
• Application Number:
  US11/052,480
• Publication Number:
  US 20060176038A1
• Time in Patent Office: 1,239 Days
• Field of Search: 323/285, 323/282, 323/222, 323/363, 323/259, 323/224, 323/225, 323/263, 323/284, 323/283, 363/17
• US Class Current: 323/259
• CPC Class Codes: H02M 3/156 with automatic control of output voltage or current, e.g. switching regulators
• CPC Class Codes: H02M 3/1582 Buck-boost converters H02M3/1584 takes precedence

Abstract

A switched regulator circuit provides step-up and step-down operation in which the level of the input voltage can be greater, equal to, or less than a preset controlled output voltage. A four switch arrangement or two switch arrangement provides buck, boost, and buck-boost regulation under constant frequency valley-peak current mode control. A single sense resistor may be utilized for sensing inductor current during only a short period during each duty cycle. As an alternative to the sense resistor, the switches themselves can be used to sense current during operation.

Claims

1. A regulator circuit for step-up and step-down operation having an input connectable to a power source and an output connectable to a load, the regulator circuit comprising:

an inductor;

a first controlled switch connected between a first inductor terminal and an input terminal;

a second controlled switch connected between the first inductor terminal and a common connection;

a third controlled switch connected between the second inductor terminal and the common connection;

a fourth controlled switch connected between the second inductor terminal and an output terminal; and

a control circuit coupled to a source of constant frequency clock cycles;

wherein

the control circuit is responsive to receipt of each clock pulse of the clock source to activate one of the controlled switches and deactivate another of the controlled switches and is responsive to current in the inductor attaining a current threshold during each clock cycle to reverse the switch activation and deactivation states for the remainder of the clock cycle.

2. A regulator circuit as recited in claim 1, wherein the control circuit comprises:

comparator circuitry;

a logic circuit connected to the comparator circuitry to receive input therefrom; and

switch driver circuitry responsive to the logic circuit for controlling the states of the controlled switches.

3. A regulator circuit as recited in claim 2, wherein the comparator circuitry comprises:

an error amplifier having a first input for receiving a voltage proportional to the voltage at the output terminal and a second input for receiving a reference potential to produce a difference signal representing the difference therebetween; and

a differential circuit responsive to the difference signal and an inductor current sensing element, the differential circuit connected to the logic circuit.

4. A voltage regulator circuit as recited in claim 1, wherein the preset voltage is greater than the input voltage and the control circuit operates in boost mode wherein:

the third switch is turned on and the fourth switch is turned off upon receipt of each clock pulse, and the third switch is turned off and the fourth switch is turned on in response to the sensed current rising to a reference threshold level;

whereby the inductor is connected in succession alternately between a common potential, via the third switch in a closed state, and the output terminal, via the fourth switch in a closed state.

5. A regulator circuit as recited in claim 1, wherein the preset voltage is less than the input voltage and the control circuit operates in buck mode wherein:

the first switch is turned off and the second switch is turned on upon receipt of each clock pulse, and the first switch is turned on and the second switch is turned off in response to the sensed current falling to a reference threshold level;

whereby the inductor is connected in succession alternately between a common potential, via the second switch in a closed state, and the input terminal, via the first switch in a closed state.

6. A regulator circuit as recited in claim 1, further comprising a sensing element for sensing inductor current connected between the common connection and a node joining the second switch and the third switch.

7. A regulator circuit as recited in claim 1, wherein inductor current is sensed at either of the second and third switches.

8. A regulator circuit for step-up and step down operation having an input connectable to a power source and an output connectable to a load, the regulator circuit comprising:

an inductor;

a first switch connected between a first inductor terminal and an input terminal;

a second switch connected between the first inductor terminal and a common connection;

a third switch connected between the second inductor terminal and the common connection;

a fourth switch connected between the second inductor terminal and an output terminal; and

a control circuit responsive to current in the inductor for controlling activation and deactivation of the switches to regulate voltage at the output to a preset voltage, wherein the control circuit comprises;

comparator circuitry;

a logic circuit connected to the comparator circuitry to receive input therefrom; and

switch driver circuitry responsive to the logic circuit for controlling the states of the switches; and

wherein the comparator circuitry comprises;

an error amplifier having a first input for receiving a voltage proportional to the voltage at the output terminal and a second input for receiving a reference potential to produce a difference signal representing the difference therebetween; and

a differential circuit responsive to the difference signal and an inductor current sensing element, the differential circuit connected to the logic circuit; and

wherein the differential circuit comprises a first circuit section for receiving a signal output from the current sensing element and a second circuit section for receiving the signal output from the current sensing element with inverted polarity.

9. A regulator circuit

for step-up and step-down operation having an input connectable to a power source and an output connectable to a load, the regulator circuit comprising:

an inductor;

a first switch connected between a first inductor terminal and an input terminal;

a second switch connected between the first inductor terminal and a common connection;

a third switch connected between the second inductor terminal and the common connection;

a fourth switch connected between the second inductor terminal and an output terminal; and

a control circuit responsive to current in the inductor and a voltage proportional to output voltage for controlling activation and deactivation of the switches to regulate voltage at the output to a preset voltage that is approximately the same as the input voltage during steady state buck-boost mode operation;

wherein

the first switch and the second switch are controlled to be in reciprocal conductive states to one another;

the third switch and the fourth switch are controlled to be in reciprocal conductive states to one another; and

the first switch and the fourth switch are in a closed state for a majority of time during each operating cycle of cycled operation; and

each operating cycle begins in response to a clock signal and, at the beginning of each cycle, the second and fourth switches are turned on for respective portions of the operating cycle followed by turn on of the first switch and turn on of the third switch for a brief portion of the same operating cycle prior to turn on of the fourth switch for the remainder of the same operating cycle.

10. A voltage regulator circuit as recited in claim 9, wherein the control circuit is coupled to a constant frequency clock source and wherein the second and fourth switches are turned on upon receipt of each clock pulse.

11. A regulator circuit

for step-up and step-down operation having an input connectable to a power source and an output connectable to a load, the regulator circuit comprising:

an inductor;

a first switch connected between a first inductor terminal and an input terminal;

a second switch connected between the first inductor terminal and a common connection;

a third switch connected between the second inductor terminal and the common connection;

a fourth switch connected between the second inductor terminal and an output terminal; and

a control circuit responsive to current in the inductor and a voltage proportional to output voltage for controlling activation and deactivation of the switches to regulate voltage at the output to a preset voltage that is approximately the same as the input voltage during steady state buck-boost mode operation;

wherein

the first switch and the second switch are controlled to be in reciprocal conductive states to one another;

the third switch and the fourth switch are controlled to be in reciprocal conductive states to one another; and

the first switch and the fourth switch are in a closed state for a majority of time during each operating cycle of cycled operation; and

each operating cycle begins in response to a clock signal and, at the beginning of each cycle, the first and third switch are turned on for respective portions of the operating cycle followed by turn on of the second switch for a brief portion of the same operating cycle and turn on of the fourth switch for the remainder of the same operating cycle.

12. A voltage regulator circuit as recited in claim 11, wherein the control circuit is coupled to a constant frequency clock source and wherein the first and third switches are turned on upon receipt of each clock pulse.