CML to CMOS signal converter

• US 7,394,283 B2
• Filed: 08/25/2006
• Issued: 07/01/2008
• Est. Priority Date: 08/25/2006
• Status: Expired due to Fees

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Sorna, Michael A., Hsu, Louis L., Gangasani, Gautam, Zier, Steven J.
• Primary Examiner(s): Tan; Vibol
• Application Number:
  US11/467,349
• Publication Number:
  US 20080061825A1
• Time in Patent Office: 676 Days
• Field of Search: 326/32, 326/86, 326/115, 326/127, 327/108
• US Class Current: 326/32
• CPC Class Codes: H03K 19/018528 with at least one differential stage

Abstract

A signal regenerator is provided which includes a common mode reference generator and a signal converter circuit. A common mode reference voltage level is generated which is variable in relation to at least one of a process used to fabricate the common mode reference generator, a level of a power supply voltage provided to the common mode reference generator or a temperature at which the common mode reference generator is operated. A signal converter circuit receives a differentially transmitted signal pair including a first input signal and a second input signal and outputs a single-ended output signal representing information carried by the differentially transmitted signal pair. Using a feedback signal from the common mode reference generator, a feedback control block controls a common mode level of the single-ended output signal in accordance with the common mode reference voltage level.

Claims

1. A method of converting a differentially transmitted signal to a single-ended rail-to-rail output signal, comprising:

generating a common mode reference voltage level which varies in relation to at least one of a process used to fabricate a generator of said common mode reference voltage level, a level of a power supply voltage provided to said common mode reference level generator or a temperature at which said common mode reference level generator is operated, said step of generating including applying the output of a first inverter back to an input of the first inverter;

receiving a differentially transmitted signal pair including a first input signal and a second input signal;

outputting a single-ended output signal representing information carried by the differentially transmitted signal pair using a second inverter to establish an upper rail voltage level and a lower rail voltage level of the single-ended output signal; and

controlling a common mode level of the first single-ended output signal in accordance with the common mode reference voltage level,

wherein the first inverter tracks variability of the at least one of a process used to fabricate, a power supply voltage or a temperature of the first inverter in a manner representative of variability of a process used to fabricate, a power supply voltage or a temperature of the second inverter.

2. The method as claimed in claim 1, wherein the common mode reference voltage level determines a switching point at which said single-ended output signal switches between a low output voltage level and a high output voltage level.

3. The method as claimed in claim 1, further comprising applying the common made reference voltage level to an intermediate node of a voltage divider to establish a predetermined relationship between the upper rail voltage level and the lower rail voltage level.

4. The method as claimed in claim 3, wherein the common mode reference voltage level establishes a voltage halfway between the upper rail voltage level and the lower rail voltage level.

5. The method as claimed in claim 1, wherein a duty cycle of the single-ended output signal is determined by the common mode reference voltage level.

6. The method as claimed in claim 1, wherein the single-ended output signal is a first single-ended output signal and the step of outputting the single-ended output signal further includes outputting a second rail-to-rail output signal which varies between the lower rail voltage level and the upper rail voltage level, wherein the first and second rail-to-rail output signals are complementary.

7. The method as claimed in claim 2, wherein the first and second input signals are input in accordance with a current mode logic (“

CML”

) signaling protocol and the output signal is output in accordance with a complementary metal oxide semiconductor (“

CMOS”

) signaling protocol.