Transferring data in a parallel processing environment

• US 7,394,288 B1
• Filed: 12/13/2005
• Issued: 07/01/2008
• Est. Priority Date: 12/13/2004
• Status: Active Grant

• Current Assignee: Massachusetts Institute of Technology
• Original Assignee: Massachusetts Institute of Technology
• Inventors: Agarwal, Anant
• Primary Examiner(s): Tran; Anh Q
• Application Number:
  US11/302,984
• Time in Patent Office: 931 Days
• Field of Search: 326/39, 326/41, 326/47, 712/11, 712/15
• US Class Current: 326/39
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 15/17381 Two dimensional, e.g. mesh, torus
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: G06F 15/80 comprising an array of processing units with common control, e.g. single instruction multiple data processors G06F15/82 takes precedence ; for correlation function computation G06F17/15
• CPC Class Codes: G06F 15/8007 single instruction multiple data [SIMD] multiprocessors
• CPC Class Codes: G06F 8/45 Exploiting coarse grain parallelism in compilation, i.e. parallelism between groups of instructions
• CPC Class Codes: G06F 9/30123 according to context, e.g. thread buffers
• CPC Class Codes: G06F 9/30189 according to execution mode, e.g. mode flag
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: H03K 19/177 arranged in matrix form
• CPC Class Codes: H03K 19/17704 the logic functions being realised by the interconnection of rows and columns
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

An integrated circuit includes a plurality of tiles. Each tile includes a processor, a switch including switching circuitry to forward data over data paths from other tiles to the processor and to switches of other tiles, and a switch memory that stores instruction streams that are able to operate independently for respective output ports of the switch.

Claims

1. An integrated circuit comprising:

a plurality of tiles, each tile comprising

a processor;

a switch including switching circuitry to forward data over data paths from other tiles to the processor and to switches of other tiles; and

a switch memory that stores instruction streams that are able to operate independently for respective output ports of the switch.

2. The integrated circuit of claim 1, wherein the switch memory extracts the instruction streams for respective output ports from an incoming macro instruction stream that includes subinstructions for the respective output ports.

3. The integrated circuit of claim 2, wherein at least some macro instructions in the macro instruction stream includes control information indicating program control flow.

4. The integrated circuit of claim 3, wherein at least some instructions in the respective instruction streams includes control information based at least in part on the control information in the corresponding macro instruction.

5. The integrated circuit of claim 1, wherein the streams include streams of at least 1,000 instructions.

6. The integrated circuit of claim 1, wherein the streams include streams of at least one billion instructions.

7. The integrated circuit of claim 1, wherein the streams include a single instruction that is repeated for multiple cycles.

8. The integrated circuit of claim 1, wherein the streams are limited by size of external virtual memory.

9. The integrated circuit of claim 1, wherein the switch memory operates as a cache.

10. The integrated circuit of claim 9, wherein, on each cache miss of the switch memory, multiple sequential instructions from a stream are fetched.

11. The integrated circuit of claim 1, wherein the instruction stream for each output port is managed by an independent program counter.

12. The integrated circuit of claim 11, wherein the program counters are able to operate in a mode in which the instruction streams are processed synchronously.

13. The integrated circuit of claim 12, wherein the mode is determined based on information in the instruction streams.

14. The integrated circuit of claim 12, wherein the mode is determined based on information in a memory that is able to be loaded by the processor.

15. The integrated circuit of claim 14, wherein the memory comprises a register.

16. An integrated circuit comprising:

a plurality of tiles each tile comprising

a pipelined processor; and

a switch including switching circuitry to forward data over data paths from other tiles to pipeline stages of the processor and to switches of other tiles

wherein a plurality of sets of one or more tiles are clocked asynchronously; and

wherein the plurality of sets of one or more tiles are each clocked at an integral multiple of a base frequency.

17. An integrated circuit comprising:

a plurality of tiles, each tile comprising

a processor; and

a switch including switching circuitry to forward data over data paths from other tiles to the processor and to switches of other tiles; and

each tile including data paths to neighboring tiles, and at least some tiles including data paths to non-neighboring tiles.

18. The integrated circuit of claim 17, wherein the plurality of tiles comprise a two-dimensional array of rectangular tiles, where each tile has at least two neighboring tiles, each neighboring tile being in a north, south, east, or west direction.

19. The integrated circuit of claim 18, wherein non-neighboring tiles of a tile comprise tiles other than a neighboring tile in the north, south, east, or west direction.