System and method for dynamically varying a clock signal
First Claim
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1. A circuit comprising:
- at least one delay element that is operable to receive a clock signal and generate a delayed clock signal having an amount of delay that varies based on an observed value of an operating voltage of said circuit;
wherein said at least one delay element receives said operating voltage and a fixed voltage, and said at least one delay element receives a track signal; and
wherein said at least one delay element comprises a pass gate that is supplied the fixed voltage if the track signal is a first value, thereby maintaining a constant amount of delay in a delayed signal output by the at least one delay element, and said pass gate is supplied the operating voltage if the track signal is a second value, thereby varying the amount of delay in the delayed signal output by the at least one delay element.
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Abstract
According to at least one embodiment, a system comprises means for performing an operation utilizing a clock signal. The system further comprises means for supplying a variable operating voltage to the performing means, and means for dynamically varying the frequency of the clock signal responsive to observed changes in the variable operating voltage.
28 Citations
29 Claims
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1. A circuit comprising:
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at least one delay element that is operable to receive a clock signal and generate a delayed clock signal having an amount of delay that varies based on an observed value of an operating voltage of said circuit; wherein said at least one delay element receives said operating voltage and a fixed voltage, and said at least one delay element receives a track signal; and
wherein said at least one delay element comprises a pass gate that is supplied the fixed voltage if the track signal is a first value, thereby maintaining a constant amount of delay in a delayed signal output by the at least one delay element, and said pass gate is supplied the operating voltage if the track signal is a second value, thereby varying the amount of delay in the delayed signal output by the at least one delay element. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A circuit comprising:
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at least one delay element that is operable to receive a clock signal and generate a delayed clock signal having an amount of delay that varies based on an observed value of an operating voltage of said circuit; a plurality of delay elements; and track control circuitry that inputs a track signal to each of said plurality of delay elements to control whether an amount of delay in a delayed signal output by the respective delay element varies based on the observed value of said operating voltage; wherein if said track signal input to one of said plurality of delay elements is a first value, that delay element varies the amount of delay in a delay signal that it outputs based on the observed value of said operating voltage, and if said track signal input to that delay element is a different value than said first value, that delay element maintains a constant delay in a delay signal that it outputs. - View Dependent Claims (13)
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14. Voltage-to-frequency conversion circuitry comprising:
at least one delay element that receives a clock signal and outputs a delayed clock signal having an amount of delay relative to the received clock signal, said at least one delay element including a transfer gate to which either a fixed voltage supply or a variable voltage supply is provided based on the value of a track signal, wherein when the variable voltage supply is provided to said transfer gate, the transfer gate varies the amount of said delay of the delayed clock signal responsive to changes in the variable voltage supply. - View Dependent Claims (15, 16, 17, 18, 19, 20)
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21. A method comprising:
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receiving a first phase of a chip'"'"'s clock signal into a delay line circuit of the chip; generating with at least one delay element of the delay line circuit a delayed clock signal having a phase that is delayed relative to the first phase of the received clock signal; comparing with comparison circuitry on the chip the generated delayed clock signal with a later phase of the chip'"'"'s clock signal, the later phase of the chip'"'"'s clock signal being later than the first phase of the chip'"'"'s clock signal; and determining with clock control circuitry on the chip whether to change the frequency of the chip'"'"'s clock signal, based at least in part on the comparison of the generated delayed clock signal with the later phase of the chip'"'"'s clock signal; wherein a plurality of delay elements are included in the delay line circuit, the method further comprising; outputting with track control circuitry on the chip a track signal for controlling which ones of the plurality of delay elements are to dynamically change their respective delay that they impart to the received clock signal responsive to observed changes in a variable operating voltage of the chip. - View Dependent Claims (22, 23, 24, 25)
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26. A method comprising:
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observing with on-chip circuitry an operating voltage of a chip; receiving a clock signal and generating a delayed clock signal having a delayed amount relative to the received clock signal with on-chip circuitry, wherein said delayed amount is programmatically selectable to vary responsive to changes in the observed operating voltage; supplying said operating voltage to the chip; supplying a fixed voltage to the chip; and selectively controlling whether a transfer gate included in the on-chip circuitry is provided the operating voltage or the fixed voltage, wherein when the transfer gate is provided the operating voltage the delayed amount of the delayed clock signal generated by the on-chip circuitry varies across a range of values observed for the operating voltage, and wherein when the transfer gate is provided the fixed voltage the delayed amount of the delayed clock signal generated by the on-chip circuitry remains constant across the range of values observed for the operating voltage. - View Dependent Claims (27)
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28. A method comprising:
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fabricating a chip that includes clock management circuitry for dynamically managing a clock signal of the chip responsive to observed changes in a variable operating voltage of the chip, wherein said clock management circuitry comprises at least one delay element, said at least one delay element receiving the chip'"'"'s clock signal and imparting an amount of delay to the received clock signal for generating a delayed clock signal; and programming the clock management circuitry on the fabricated chip to tailor its sensitivity to said observed changes in the chip'"'"'s variable operating voltage, wherein said programming comprises selectively controlling whether a transfer gate included in the at least one delay element is provided the variable operating voltage or a fixed voltage, wherein if the transfer gate is provided the variable operating voltage the delayed amount of the delayed clock signal generated by the at least one delay element varies across a range of values observed for the operating voltage, and wherein if the transfer gate is provided the fixed voltage the delayed amount of the delayed clock signal generated by the at least one delay element remains constant across the range of values observed for the operating voltage. - View Dependent Claims (29)
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Specification