Column select multiplexer circuit for a domino random access memory array

• US 7,394,681 B1
• Filed: 11/14/2005
• Issued: 07/01/2008
• Est. Priority Date: 11/14/2005
• Status: Active Grant

• Current Assignee: Intellectual Ventures Funding LLC (Intellectual Ventures LLC)
• Original Assignee: Transmeta Corporation (Novafora, Inc.)
• Inventors: Masleid, Robert P.
• Primary Examiner(s): PHUNG, ANH K
• Application Number:
  US11/273,897
• Time in Patent Office: 960 Days
• Field of Search: 365/154, 365/189.02, 365/156, 365/230.05
• US Class Current: 365/154
• CPC Class Codes: G11C 11/413 Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction

Abstract

A column select multiplexer circuit for a domino random access memory array including a plurality of column selector circuits for selecting a column from a plurality of columns of static random access memory cells.

Claims

1. A column select multiplexer circuit in a compound domino configuration for a domino random access memory array, comprising:

a first column select multiplexer responsive to a first column select signal for selecting a first column of static random access memory cells (SRAM cells) from a first plurality of columns of SRAM cells;

a second column select multiplexer responsive to a second column select signal for selecting a second column of SRAM cells from a second plurality of columns of SRAM cells; and

a NAND logic gate coupled as a first input to a first output from said first column select multiplexer and as a second input to a second output from said second column select multiplexer, said NAND logic gate outputting a data out signal from an SRAM cell in said first or second plurality of columns of SRAM cells.

2. The column select multiplexer circuit of claim 1, wherein said first column select multiplexer comprises:

a plurality of column selector circuits for selecting said first plurality of columns of SRAM cells, wherein each of said plurality of column selector circuits comprises;

a bitline precharge circuit for precharging a bitline and a bitline bar of said first column of SRAM cells, said bitline precharge circuit coupled to said bitline and said bitline bar;

a first access n-type field effect transistor (NFET) coupled to said bitline and to a first access node for accessing said bitline;

a second access NFET coupled to said bitline bar and to a second node for accessing said bitline bar;

a column select line coupled to said first and second access NFETs that when activated selects said first column of SRAM cells for reading and writing of a selected SRAM cell.

3. The column select multiplexer circuit of claim 1, wherein said first column select multiplexer and said second column select multiplexer are configured between said first plurality of columns of SRAM cells and said second plurality of columns of SRAM cells to subdivide a capacitance associated with said column select multiplexer circuit.

4. The column select multiplexer circuit of claim 1, further comprising:

a noise suppression circuit coupled to said first column select multiplexer, said noise suppression circuit comprising a first transistor cross-coupled to a second transistor through first and second access transistors providing access to a bitline and bit line bar of a selected column of SRAM cells.

5. The column select multiplexer circuit of claim 1, further comprising:

a noise suppression circuit coupled to said second column select multiplexer, said noise suppression circuit comprising a first transistor cross-coupled to a second transistor through first and second access transistors providing access to a bitline and bit line bar of a selected column of SRAM cells.

6. The column select multiplexer circuit of claim 1, further comprising:

a first write circuit coupled to said first column select multiplexer for writing to a first selected SRAM cell in said first column of SRAM cells; and

a second write circuit coupled to said second column select multiplexer for writing to a second selected SRAM cell in said second column of SRAM cells.

7. The column select multiplexer circuit of claim 1, further comprising:

an NFET coupled to an output of said NAND logic gate for outputting said data out signal.

8. Column select multiplexer means for a domino random access memory array, comprising:

first column select means responsive to a first column select signal for selecting a first column of static random access memory cells (SRAM cells) from a first plurality of columns of SRAM cells;

second column select means responsive to a second column select signal for selecting a second column of SRAM cells from a second plurality of columns of SRAM cells; and

NAND logic means coupled as a first input to a first output from said first column select means and as a second input to a second output from said second column select means, said NAND logic means for outputting a data out signal from an SRAM cell in said first or second plurality of columns of SRAM cells.

9. The column select means of claim 8, wherein said first column select means comprises:

a plurality of column selector means for selecting said first plurality of columns of SRAM cells, wherein each of said plurality of column selector means comprises;

bitline precharge means for precharging a bitline and a bitline bar of said first column of SRAM cells, said bitline precharge means coupled to said bitline and said bitline bar;

first access means coupled to said bitline and to a first access node for accessing said bitline;

second access means coupled to said bitline bar and to a second node for accessing said bitline bar;

column select line means coupled to said first and second access means that when activated selects said first column of SRAM cells for reading and writing of a selected SRAM cell.

10. The column select means of claim 8, wherein said first column select means and said second column select means are configured between said first plurality of columns of SRAM cells and said second plurality of columns of SRAM cells for subdividing a capacitance associated with said column select means.

11. The column select means circuit of claim 8, further comprising:

noise suppression means coupled to said first column select means, said noise suppression means comprising a first transistor means cross-coupled to a second transistor means through first and second access transistor means for providing access to a bitline and bit line bar of a selected column of SRAM cells.

12. The column select means circuit of claim 8, further comprising:

noise suppression means coupled to said second column select means, said noise suppression means comprising a first transistor means cross-coupled to a second transistor means through first and second access transistor means for providing access to a bitline and bit line bar of a selected column of SRAM cells.

13. The column select means circuit of claim 8, further comprising:

a first write means coupled to said first column select means for writing to a first selected SRAM cell in said first column of SRAM cells; and

a second write means coupled to said second column select means for writing to a second selected SRAM cell in said second column of SRAM cells.

14. The column select means circuit of claim 8, further comprising:

n-type field effect transistor means coupled to an output of said NAND means for outputting said data out signal.