Programmable structure including discontinuous storage elements and spacer control gates in a trench

• US 7,394,686 B2
• Filed: 07/25/2005
• Issued: 07/01/2008
• Est. Priority Date: 07/25/2005
• Status: Expired due to Fees

• Current Assignee: North Star Innovations Inc. (Wi-LAN Inc.)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Swift, Craig T., Chindalore, Gowrishankar L.
• Primary Examiner(s): Elms, Richard T.
• Assistant Examiner(s): Sofocleous, Alexander
• Application Number:
  US11/188,585
• Publication Number:
  US 20070018221A1
• Time in Patent Office: 1,072 Days
• Field of Search: 257/242, 365/185.28, 365/185.03, 365/185.18
• US Class Current: 365/185.03
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/42332 with the floating gate formed by two or more non connected parts, e.g. multi-particles flating gate
• CPC Class Codes: H01L 29/42336 with one gate at least partly formed in a trench
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A semiconductor storage cell includes first and second source/drain regions underlying first and second trenches defined in a semiconductor substrate. Sidewalls of the trenches are lined with a charge storage stack that includes a layer of discontinuous storage elements (DSEs), which are preferably silicon nanocrystals. Spacer control gates are located in the trenches adjacent to the charge storage stacks on the trench sidewalls. The trench depth exceeds the spacer height so that a gap exists between a top of the spacers and the top of the substrate. A continuous select gate layer overlies the first trench. The gap facilitates ballistic programming of the DSEs adjacent to the gap by accelerating electrons traveling substantially perpendicular to the trench sidewalls. The storage cell may employ hot carrier injection programming to program a portion of the DSEs proximal to the source/drain regions.

Claims

1. An array of storage cells wherein at least one of the storage cells comprises;

a first source/drain region underlying a first trench defined in a semiconductor substrate;

a second source/drain region underlying a second trench in the substrate;

a charge storage stack on sidewalls of the trenches wherein the charge storage stack includes a layer of discontinuous storage elements (DSEs); and

electrically conductive spacers formed in the first and second trenches adjacent to the charge storage stacks wherein the depth of the trenches exceeds a height of the spacers wherein a gap exists between a top of the spacers and an upper surface of the substrate.

2. The storage array of claim 1, wherein the DSEs include silicon nanocrystals.

3. The storage array of claim 2, further comprising a continuous control gate running perpendicular to the first and second trenches and traversing the first and second trenches.

4. The storage array of claim 3, further comprising a first diffusion region on a first side of the control gate and a second diffusion region on a second side of the control gate.

5. The storage array of claim 4, wherein the first and second diffusion regions are equidistant between the first and second trenches.

6. The storage array of claim 4, wherein the first and second diffusion regions are diagonally placed with the first diffusion region is proximal to the first trench and the second diffusion region is proximal to the second trench.

7. The storage array of claim 2, further comprising a first control gate comprising a continuous control gate overlying and running parallel to the first trench and a second control gate comprising a continuous control gate overlying and running parallel with the second trench.

8. The storage array of claim 7, further comprising a diffusion region bordered on first and second sides by the first and second gates.

9. The storage array of claim 8, further wherein the diffusion region is bordered on third and fourth sides by isolation regions.

10. The storage array of claim 8, wherein the diffusion region is a continuous region extending across the array running parallel to the source/drain regions.

11. A method of programming a first bit of storage cell in an array of storage cells by injecting charge into a first injection region of the storage cell, comprising:

biasing a first source/drain region underlying a first trench in a semiconductor substrate to a first programming voltage (V_P1);

biasing a second source/drain region to a fourth programming voltage (V_P4);

biasing a first conductive spacer adjacent to a first layer of discontinuous storage elements (DSEs) on a sidewall of the first trench to a second programming voltage (V_P2) wherein a depth of the trench exceeds a height of the spacer wherein a gap is defined from a top of the spacer to a top of the substrate; and

biasing a first select gate overlying the first trench to a third programming voltage (V_P3).

12. The method of claim 11, further comprising biasing a semiconductor layer in which the first and second source/drain regions reside to 0 V.

13. The method of claim 12, wherein biasing the second source/drain region comprises biasing a second source drain region underlying a second trench in the substrate, wherein the second trench is lined with a layer of DSEs.

14. The method of claim 13, wherein biasing the first select gate comprises biasing a continuous select gate running perpendicular to the first and second trenches and traversing the first and second trenches.

15. The method of claim 12, wherein biasing the second source/drain region comprises biasing a diffusion region occupying an upper portion of the substrate between the first trench and a second trench.

16. The method of claim 15, wherein biasing the first select gate comprises biasing a continuous select gate overlying the first trench and running parallel to the first trench.

17. The method of claim 15, wherein biasing the second source/drain regions comprises biasing a first diffusion region occupying an upper portion of the substrate on a first side of the first control gate running perpendicular to the source/drain trenches.

18. The method of claim 17, further comprising programming a second bit of the storage cell by injecting charge into a second injection region of the DSEs, including biasing a third source/drain region occupying an upper portion of the substrate on a second side of the first select gate.

19. A programmable storage cell, comprising:

a semiconductor substrate defining first and second trenches running parallel to each other;

first and second source/drain regions underlying the first and second trenches, respectively;

charge storage stacks lining sidewalls of the trenches;

control gates formed in the first and second trenches adjacent to the charge storage stacks wherein the depth of the trenches exceeds a height of the control gates wherein a gap exists between a top of the control gates and an upper surface of the substrate;

a first select gate overlying the first trench;

a first diffusion region occupying an upper portion of the substrate between the first and second trenches.

20. The storage device of claim 19, wherein the diffusion region extends across an array parallel to the first and second source/drain regions.