Memory system comprising memories with different capacities and storing and reading method thereof

• US 7,394,715 B1
• Filed: 01/11/2006
• Issued: 07/01/2008
• Est. Priority Date: 01/11/2006
• Status: Expired due to Fees

• Current Assignee: MediaTek, Inc.
• Original Assignee: MediaTek, Inc.
• Inventors: Tseng, Jui-Hsing
• Primary Examiner(s): Dinh; Son
• Assistant Examiner(s): NGUYEN, NAM THANH
• Application Number:
  US11/306,771
• Time in Patent Office: 902 Days
• Field of Search: 365/230.03, 365/221, 365/189.01, 365/189.011, 711/179
• US Class Current: 365/230.03
• CPC Class Codes: G06F 12/06 Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication G06F12/08 takes precedence
• CPC Class Codes: G06F 12/0623 for memory modules

Abstract

A memory system includes a first memory, a second memory, a determining unit, and an accessing unit. The capacity of the second memory is different from the capacity of the first memory. The first and the second memories are virtually partitioned into a first section and a second section. The determining unit determines to which of the first and the second sections an address corresponds, the address being associated with data to be transferred. The accessing unit is coupled to the determining unit and the first and second memories for transferring the data to or from the first memory and a first portion of the second memory when the determining unit determines that the address corresponds to the first section; and for transferring the data to or from a second portion of the second memory when the determining unit determines that the address corresponds to the second section.

Claims

1. A storing method for a memory system comprising a first section and a second section, the first section comprising a first memory and a first portion of a second memory, the second section comprising a second portion of the second memory, the first memory having a first data bus, the second memory having a second data bus different from the first data bus, the method comprising:

receiving data and an address associated therewith;

determining to which of the first and the second sections the address corresponds;

if the address corresponds to the first section, storing the data into the first section; and

if the address corresponds to the second section, storing the data into the second section.

2. The method of claim 1, wherein storing the data into the first section comprises:

simultaneously storing a first part of the data into the first memory and storing a second part of the data into the first portion of the second memory.

3. The method of claim 1, wherein storing the data into the second section comprises:

sequentially storing a first part and a second part of the data into the second portion of the second memory.

4. The method of claim 3, wherein storing the data into the second section further comprises:

providing a control signal to prevent the data from being stored into the first section.

5. A reading method for a memory system comprising a first section and a second section, the first section comprising a first memory and a first portion of a second memory, the second section comprising a second portion of the second memory, the first memory having a first data bus, the second memory having a second data bus different from the first data bus, the method comprising:

receiving an address;

determining to which of the first and the second sections the address corresponds;

if the address corresponds to the first section, reading data from the first section; and

if the address corresponds to the second section, reading data from the second section.

6. The method of claim 5, wherein reading the data from the first section comprises:

simultaneously reading a first part of the data from the first memory and reading a second part of the data from the first portion of the second memory.

7. The method of claim 5, wherein reading the data from the second section comprises:

sequentially reading a first part and a second part of the data from the second portion of the second memory.

8. The method of claim 7, wherein reading the data from the second section further comprises:

providing a control signal to latch the first part of the data until the data is completely read from the second section.

9. A memory system comprising:

a first memory having a first data bus;

a second memory having a second data bus different from the first data bus, the capacity of the second memory being different from the capacity of the first memory, the first and the second memories being virtually partitioned into a first section and a second section;

a determining unit for determining to which of the first and the second sections an address corresponds, the address being associated with data to be transferred; and

an accessing unit coupled to the determining unit, the first memory, and the second memory, for transferring the data to or from the first memory and a first portion of the second memory via the first and second data buses respectively when the determining unit determines that the address corresponds to the first section, and for transferring the data to or from a second portion of the second memory via the second data bus when the determining unit determines that the address corresponds to the second section.

10. The memory system of claim 9, wherein the accessing unit simultaneously stores a first part of the data into the first memory and stores a second part of the data into the first portion of the second memory when the determining unit determines that the address corresponds to the first section.

11. The memory system of claim 9, wherein the accessing unit sequentially stores a first part and a second part of the data into the second portion of the second memory when the determining unit determines that the address corresponds to the second section.

12. The memory system of claim 11, wherein when the determining unit determines that the address corresponds to the second section, the accessing unit provides a control signal to prevent the data from being stored into the first section.

13. The memory system of claim 9, wherein the accessing unit simultaneously reads a first part of the data from the first memory and reads a second part of the data from the first portion of the second memory when the determining unit determines that the address corresponds to the first section.

14. The memory system of claim 9, wherein the accessing unit sequentially reads a first part and a second part of the data from the second portion of the second memory when the determining unit determines that the address corresponds to the second section.

15. The memory system of claim 14, wherein when the determining unit determines that the address corresponds to the second section, the accessing unit provides a control signal to latch the first part of the data until the data is completely read from the second section.

16. The memory system of claim 9, wherein the first section comprises the first memory and the first portion of the second memory, and the second section comprises the second portion of the second memory.