Using a transactional execution mechanism to free up processor resources used by a busy-waiting thread
First Claim
1. A method for improving the performance of a processor that supports speculative execution, wherein when a first thread encounters a halt sequence which is used by the first thread to wait for data that is to be generated by a second thread, the method comprises:
- starting a transactional memory operation by generating a checkpoint and entering transactional-execution mode, wherein instructions are speculatively executed but results are not committed to the architectural state of the processor until the transaction completes without interference;
loading from a mailbox address associated with the halt sequence so that a transactional memory system can detect a subsequent interference with the load from the mailbox address, wherein the subsequent interference with the load from the mailbox address indicates that the halt sequence is to be terminated; and
while executing in a speculative-execution mode, stalling execution of the first thread, so that the processor does not execute instructions within the halt sequence, thereby freeing up processor resources for other threads;
wherein when the second thread has completed generating the data required by the first thread, the second thread performs a store operation to the mailbox address and a transactional-memory mechanism within the processor terminates the halt sequence by;
detecting an interference with the load from the mailbox address;
exiting the halt sequence; and
continuing execution of instructions following the halt sequence.
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Accused Products
Abstract
A technique for improving the performance of a system that supports simultaneous multi-threading (SMT). When a first thread encounters a halt sequence, the system starts a transactional memory operation by generating a checkpoint and entering a transactional-execution mode. Next, the system loads from a mailbox address associated with the halt sequence. The system then stalls execution of the first thread, so that the first thread does not execute instructions within the halt sequence, thereby freeing up processor resources for other threads. To terminate the halt sequence, a second thread stores to the mailbox address, which causes a transactional-memory mechanism within the processor to detect an interference with the previous load from the mailbox address by the first thread and which causes the first thread to exit from the halt sequence. The system then continues executing instructions following the halt sequence.
32 Citations
15 Claims
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1. A method for improving the performance of a processor that supports speculative execution, wherein when a first thread encounters a halt sequence which is used by the first thread to wait for data that is to be generated by a second thread, the method comprises:
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starting a transactional memory operation by generating a checkpoint and entering transactional-execution mode, wherein instructions are speculatively executed but results are not committed to the architectural state of the processor until the transaction completes without interference; loading from a mailbox address associated with the halt sequence so that a transactional memory system can detect a subsequent interference with the load from the mailbox address, wherein the subsequent interference with the load from the mailbox address indicates that the halt sequence is to be terminated; and while executing in a speculative-execution mode, stalling execution of the first thread, so that the processor does not execute instructions within the halt sequence, thereby freeing up processor resources for other threads; wherein when the second thread has completed generating the data required by the first thread, the second thread performs a store operation to the mailbox address and a transactional-memory mechanism within the processor terminates the halt sequence by; detecting an interference with the load from the mailbox address; exiting the halt sequence; and continuing execution of instructions following the halt sequence. - View Dependent Claims (2, 3, 4, 5)
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6. An apparatus for improving the performance of a processor that supports speculative execution, comprising:
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an processing mechanism configured such that when a first thread encounters a halt sequence which is used by the first thread to wait for data that is to be generated by a second thread, the processing mechanism; starts a transactional memory operation using a transactional-memory mechanism which involves generating a checkpoint and entering transactional-execution mode, wherein instructions are speculatively executed but results are not committed to the architectural state of the processor until the transaction completes without interference; loads from a mailbox address associated with the halt sequence so that a transactional memory system can detect a subsequent interference with the load from the mailbox address, wherein the subsequent interference with the load from the mailbox address indicates that the halt sequence is to be terminated; and while executing in a speculative-execution mode, stalls execution of the first thread, so that the processor does not execute instructions within the halt sequence, thereby freeing up processor resources for other threads; wherein when the second thread has completed generating the data required by the first thread, the second thread performs a store operation to the mailbox address and the transactional-memory mechanism within the processing mechanism is configured to; detect an interference with the load from the mailbox address; exit the halt sequence; and
tocontinue execution of instructions following the halt sequence, thereby terminating the halt sequence. - View Dependent Claims (7, 8, 9, 10)
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11. A computer system for improving the performance of a processor that supports speculative execution, comprising:
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the processor; a memory; and a transactional-memory mechanism; wherein when a first thread encounters a halt sequence which is used by the first thread to wait for data that is to be generated by a second thread, the processor is configured to; start a transactional memory operation using the transactional-memory mechanism which involves generating a checkpoint and entering transactional-execution mode, wherein instructions are speculatively executed but results are not committed to the architectural state of the processor until the transaction completes without interference; load from a mailbox address associated with the halt sequence so that a transactional memory system can detect a subsequent interference with the load from the mailbox address wherein the subsequent interference with the load from the mailbox address indicates that the halt sequence is to be terminated; and while executing in a speculative-execution mode, stall execution of the first thread, so that the processor does not execute instructions within the halt sequence, thereby freeing up processor resources for other threads; wherein when the second thread has completed generating the data required by the first thread, the second thread performs a store operation to the mailbox address and the transactional-memory mechanism within the processing mechanism is configured to; detect an interference with the load from the mailbox address; exit the halt sequence; and
tocontinue execution of instructions following the halt sequence, thereby terminating the halt sequence. - View Dependent Claims (12, 13, 14, 15)
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Specification