Common circuitry supporting both bit node and check node processing in LDPC (Low Density Parity Check) decoder
First Claim
1. A decoder that is operable to decode an LDPC (Low Density Parity Check) coded signal, the decoder comprising:
- a FIFO (First-In First-Out) buffer that is operable to receive and subsequently to provide a plurality of edge messages with respect to a plurality of check nodes;
a bit node processing functional block that is operable to receive a bit metric that corresponds to a symbol of the LDPC coded signal, the plurality of edge messages with respect to the plurality of check nodes, and one edge message of the plurality of edge messages with respect to the plurality of check nodes from the FIFO buffer, and that comprises;
an accumulator that is operable to add each edge message of the plurality of edge messages with respect to the plurality of check nodes with the bit metric thereby generating a summed value; and
a subtraction functional block that is operable to subtract the one edge message of the plurality of edge messages with respect to the plurality of check nodes provided from the FIFO buffer from the summed value thereby generating one updated edge message of a plurality of updated edge messages with respect to a plurality of bit nodes;
wherein the FIFO buffer is also operable to receive and subsequently to provide the plurality of updated edge messages with respect to the plurality of bit nodes; and
a check node processing functional block that is operable to receive the plurality of updated edge messages with respect to the plurality of bit nodes from the bit node processing functional block and that comprises;
a min** (min-double-star) processing functional block that is operable to perform min** processing using the plurality of updated edge messages with respect to the plurality of bit nodes thereby generating a min** resultant; and
a min**−
(min-double-star-minus) processing functional block that is operable to perform min**−
processing using one updated edge message with respect to the plurality of bit nodes provided from the FIFO buffer and the min** resultant received from the min** processing functional block thereby generating an updated edge message with respect to the plurality of check nodes.
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Abstract
Common circuitry supporting both bit node and check node processing in LDPC (Low Density Parity Check) decoder. A novel approach is presented by which a decoder may use the same circuitry to perform updating of edge messages with respect to bit nodes as well as updating of edge messages with respect to check nodes in the context of decoding LDPC coded signals. In addition, several very efficient architectures are presented to performing check node processing that involves the updating of edge messages with respect to check nodes. One embodiment performs check node processing using min** (min-double-star) processing in conjunction with min**− (min-double-star-minus) processing. Another embodiment performs check node processing using min†† (min-double-dagger) processing in conjunction with min†− (min-dagger-minus) processing. In addition, a single FIFO may be implemented to service a number of macro blocks in a parallel decoding implementation.
33 Citations
20 Claims
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1. A decoder that is operable to decode an LDPC (Low Density Parity Check) coded signal, the decoder comprising:
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a FIFO (First-In First-Out) buffer that is operable to receive and subsequently to provide a plurality of edge messages with respect to a plurality of check nodes; a bit node processing functional block that is operable to receive a bit metric that corresponds to a symbol of the LDPC coded signal, the plurality of edge messages with respect to the plurality of check nodes, and one edge message of the plurality of edge messages with respect to the plurality of check nodes from the FIFO buffer, and that comprises; an accumulator that is operable to add each edge message of the plurality of edge messages with respect to the plurality of check nodes with the bit metric thereby generating a summed value; and a subtraction functional block that is operable to subtract the one edge message of the plurality of edge messages with respect to the plurality of check nodes provided from the FIFO buffer from the summed value thereby generating one updated edge message of a plurality of updated edge messages with respect to a plurality of bit nodes; wherein the FIFO buffer is also operable to receive and subsequently to provide the plurality of updated edge messages with respect to the plurality of bit nodes; and a check node processing functional block that is operable to receive the plurality of updated edge messages with respect to the plurality of bit nodes from the bit node processing functional block and that comprises; a min** (min-double-star) processing functional block that is operable to perform min** processing using the plurality of updated edge messages with respect to the plurality of bit nodes thereby generating a min** resultant; and a min**−
(min-double-star-minus) processing functional block that is operable to perform min**−
processing using one updated edge message with respect to the plurality of bit nodes provided from the FIFO buffer and the min** resultant received from the min** processing functional block thereby generating an updated edge message with respect to the plurality of check nodes. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A decoder that is operable to decode an LDPC (Low Density Parity Check) coded signal, the decoder comprising:
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a FIFO (First-In First-Out) buffer that is operable to receive and subsequently to provide a plurality of edge messages with respect to a plurality of check nodes; a bit node processing functional block that is operable to receive a bit metric that corresponds to a symbol of the LDPC coded signal, the plurality of edge messages with respect to the plurality of check nodes, and one edge message of the plurality of edge messages with respect to the plurality of check nodes from the FIFO buffer, and that comprises; an accumulator that is operable to add each edge message of the plurality of edge messages with respect to the plurality of check nodes with the bit metric thereby generating a summed value; and a subtraction functional block that is operable to subtract the one edge message of the plurality of edge messages with respect to the plurality of check nodes provided from the FIFO buffer from the summed value thereby generating one updated edge message of a plurality of updated edge messages with respect to a plurality of bit nodes; wherein the FIFO buffer is also operable to receive and subsequently to provide absolute values of each updated edge message of the plurality of updated edge messages with respect to the plurality of bit nodes; and a check node processing functional block that is operable to receive the plurality of updated edge messages with respect to the plurality of bit nodes from the bit node processing functional block and that comprises; a min†
†
(min-double-dagger) processing functional block that is operable to perform min†
†
processing thereby generating a min* (min-star) resultant generated using the plurality of updated edge message with respect to the plurality of bit nodes and also thereby outputting a minimum updated edge message of the plurality of updated edge message with respect to the plurality of bit nodes; anda min†
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(min-dagger-minus) processing functional block that is operable to perform min†
−
processing using an absolute value of one updated edge message of the plurality of updated edge messages with respect to the plurality of bit nodes provided from the FIFO buffer, the min* resultant received from the min†
†
processing functional block, and the minimum updated edge message received from the min†
†
processing functional block thereby generating an updated edge message with respect to the plurality of check nodes. - View Dependent Claims (13, 14, 15, 16, 17, 18)
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19. A decoder, comprising a plurality of macro blocks that is arranged in a parallel configuration such that each macro block of the plurality of macro blocks comprises one FIFO (First-In First-Out) buffer and a plurality of bit/check processors, that is operable to decode an LDPC (Low Density Parity Check) coded signal, wherein:
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the FIFO buffer of each macro block of the plurality of macro blocks is operable to receive and subsequently to provide a plurality of edge messages with respect to the plurality of check nodes; the FIFO buffer of each macro block of the plurality of macro blocks includes a plurality of parallel paths such that each parallel path corresponds to one bit/check processor of the corresponding plurality of bit/check processors; each bit/check processor of the plurality of bit/check processors comprises a corresponding bit node processing functional block and a corresponding check node processing functional block, wherein; each corresponding bit node processing functional block is operable to receive a bit metric that corresponds to a symbol of the LDPC coded signal, the plurality of edge messages with respect to the plurality of check nodes, and one edge message of the plurality of edge messages with respect to the plurality of check nodes from the FIFO buffer, and comprises; an accumulator that is operable to add each edge message of the plurality of edge messages with respect to the plurality of check nodes with the bit metric thereby generating a summed value; and a subtraction functional block that is operable to subtract the one edge message of the plurality of edge messages with respect to the plurality of check nodes provided from the FIFO buffer from the summed value thereby generating one updated edge message of a plurality of updated edge messages with respect to a plurality of bit nodes; the FIFO buffer of each macro block of the plurality of macro blocks is also operable to receive and subsequently to provide the plurality of updated edge messages with respect to the plurality of bit nodes; and each check node processing functional block is operable to receive the plurality of updated edge messages with respect to the plurality of bit nodes from a corresponding bit node processing functional block and comprises; a min** (min-double-star) processing functional block that is operable to perform min** processing using the plurality of updated edge messages with respect to the plurality of bit nodes thereby generating a min** resultant; and a min**−
(min-double-star-minus) processing functional block that is operable to perform min**−
processing using one updated edge message with respect to the plurality of bit nodes provided from the FIFO buffer and the min** resultant received from the min** processing functional block thereby generating an updated edge message with respect to the plurality of check nodes.
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20. A decoder, comprising a plurality of macro blocks that is arranged in a parallel configuration such that each macro block of the plurality of macro blocks comprises one FIFO (First-In First-Out) buffer and a plurality of bit/check processors, that is operable to decode an LDPC (Low Density Parity Check) coded signal, wherein:
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the FIFO buffer of each macro block of the plurality of macro blocks is operable to receive and subsequently to provide a plurality of edge messages with respect to the plurality of check nodes; the FIFO buffer of each macro block of the plurality of macro blocks includes a plurality of parallel paths such that each parallel path corresponds to one bit/check processor of the corresponding plurality of bit/check processors; each bit/check processor of the plurality of bit/check processors comprises a corresponding bit node processing functional block and a corresponding check node processing functional block, wherein; each corresponding bit node processing functional block is operable to receive a bit metric that corresponds to a symbol of the LDPC coded signal, the plurality of edge messages with respect to the plurality of check nodes, and one edge message of the plurality of edge messages with respect to the plurality of check nodes from the FIFO buffer, and comprises; an accumulator that is operable to add each edge message of the plurality of edge messages with respect to the plurality of check nodes with the bit metric thereby generating a summed value; and a subtraction functional block that is operable to subtract the one edge message of the plurality of edge messages with respect to the plurality of check nodes provided from the FIFO buffer from the summed value thereby generating one updated edge message of a plurality of updated edge messages with respect to a plurality of bit nodes; the FIFO buffer of each macro block of the plurality of macro blocks is also operable to receive and subsequently to provide absolute values of each updated edge message of the plurality of updated edge messages with respect to the plurality of bit nodes; and each check node processing functional block is operable to receive the plurality of updated edge messages with respect to the plurality of bit nodes from a corresponding bit node processing functional block and comprises; a min†
†
(min-double-dagger) processing functional block that is operable to perform min†
†
processing thereby generating a min* (min-star) resultant generated using the plurality of updated edge message with respect to the plurality of bit nodes and also thereby outputting a minimum updated edge message of the plurality of updated edge message with respect to the plurality of bit nodes; anda min†
−
(min-dagger-minus) processing functional block that is operable to perform min†
−
processing using an absolute value of one updated edge message of the plurality of updated edge messages with respect to the plurality of bit nodes provided from the FIFO buffer, the min* resultant received from the min†
†
processing functional block, and the minimum updated edge message received from the min†
†
processing functional block thereby generating an updated edge message with respect to the plurality of check nodes.
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Specification