Manufacturing aware design and design aware manufacturing

• US 7,395,516 B2
• Filed: 08/28/2005
• Issued: 07/01/2008
• Est. Priority Date: 05/20/2005
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Scheffer, Louis K., Fujimura, Akira
• Primary Examiner(s): Whitmore; Stacy
• Assistant Examiner(s): ROSSOSHEK, YELENA
• Application Number:
  US11/214,472
• Publication Number:
  US 20060265682A1
• Time in Patent Office: 1,038 Days
• Field of Search: 716/4, 716/6, 716/8, 716/10, 716/19, 716/21, 702/2, 430/5, 430/30, 430/394, 355/53, 355/67, 355/71
• US Class Current: 716/54
• CPC Class Codes: G03F 7/70125 Use of illumination settings tailored to particular mask patterns details of setting means G03F7/70091

Abstract

Some embodiments of the invention provide a process for designing and manufacturing an integrated circuit (“IC”). The process selects a wiring configuration and an illumination configuration. The process uses the selected wiring configuration to design an IC layout. The process then uses the selected illumination configuration to manufacture the IC based on the designed IC layout. Some embodiments concurrently select an optimal pair of wiring and illumination configurations. Other embodiments select an illumination configuration based on the selected wiring configuration. Yet other embodiments select a wiring configuration based on the selected illumination configuration. In some embodiments, selecting the illumination configuration entails selecting at least one stepper lens for the IC layout, where the stepper lens illuminates at least one mask for at least one particular layer of the IC layout. In some embodiments, this selection entails selecting a stepper lens for each particular layer of the IC layout. Also, in some embodiments, selecting the wiring configuration entails defining the width and/or spacing of the routes along different directions on at least one particular wiring layer of the IC layout. In some embodiments, this selection entails selecting width and/or spacing of routes along different directions on each particular layer of the IC layout.

Claims

1. A design aware process for manufacturing an integrated circuit (“

IC”

), the process comprising;

a. concurrently identifying (i), based on a fabrication technology, an illumination configuration to be used in manufacturing the IC, and (ii) based on a wiring model, dimensional attributes of a plurality of routes for use in an IC layout;

b. after the concurrent identification of the illumination configuration and dimensional attributes, utilizing software tools to design the IC layout based on the identified dimensional attributes of the plurality of routes; and

c. using the identified illumination configuration to manufacture the IC based on the designed IC layout.

2. The process of claim 1, wherein the concurrent identification of the illumination configuration and dimensional attributes is iteratively performed.

3. The process of claim 1, wherein identifying the dimensional attributes comprises:

identifying a first spacing constraint for routes in a first plurality of routes along a first direction of a first layer of the IC layout; and

identifying a second spacing constraint for routes in a second plurality of routes along a second direction of the first layer of the IC layout.

4. The process of claim 1, wherein identifying the dimensional attributes comprises:

identifying a first width for each route in a first plurality of routes along a first direction of a first layer of the IC layout; and

identifying a second width for each route in a second plurality of routes along a second direction of the first layer of the IC layout.

5. The process of claim 4 further comprising identifying a third plurality of routes, each route in the third plurality of routes comprising a third width.

6. The process of claim 5, wherein routes that have the third width are in a different region of the IC layout than routes that have the first width.

7. The process of claim 4, wherein the identified dimensional attributes are based on a desired manufacturing yield.

8. The process of claim 7, wherein the first width is inversely proportional to the desired manufacturing yield.

9. The process of claim 4, wherein the first width is narrower than the second width.

10. The process of claim 9, wherein identifying the illumination configuration comprises selecting a dipole lens for the first layer of the IC layout.

11. The process of claim 10, wherein the first direction is a vertical direction, wherein the dipole lens includes horizontally aligned poles.

12. The process of claim 10, wherein the first direction is a horizontal direction, wherein the dipole lens includes vertically aligned poles.

13. The process of claim 10, wherein the first direction a 45°

diagonal direction, wherein the dipole lens includes 135°

aligned poles.

14. The process of claim 1, wherein identifying the illumination configuration comprises identifying a stepper lens for each layer of the IC layout.