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Switched resonant ultrasonic power amplifier system

  • US 7,396,336 B2
  • Filed: 10/27/2004
  • Issued: 07/08/2008
  • Est. Priority Date: 10/30/2003
  • Status: Active Grant
First Claim
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1. A system for controlling an output of a surgical ultrasonic device, the system comprising:

  • a switched resonant power amplifier receiving and processing a driver output signal for generating a drive signal that is provided to an ultrasonic device for controlling the output of the ultrasonic device;

    an output control circuit comprising;

    a wave shaping circuit comprising;

    a zero crossing detector receiving and processing a feedback signal related to the output of the ultrasonic device and generated by the ultrasonic device, the zero crossing detector generating a corresponding square wave signal; and

    a comparator comparing the square wave signal to a reference signal for generating a reset signal having a substantially identical frequency to the feedback signal;

    a compensating circuit comprising;

    a reference timer for receiving and processing the reset signal for generating a compensated reference signal having substantially the same frequency as the reset signal and substantially 180°

    out-of-phase with respect to the reset signal, wherein frequency and amplitude characteristics of the compensated reference signal are determined at least by the reset signal; and

    a phase locked loop (PLL) receiving first and second input signals, wherein the first input signal is the compensated reference signal and the second input signal is a divider reference signal, and wherein the PLL processes the first and second input signals for generating a compensated clock signal that is adjusted for at least one of phase and frequency differences between the received first and second input signals; and

    a compensated drive circuit operatively coupled to the compensating circuit, the compensated drive circuit comprising;

    divider circuitry for stepping down the frequency of the compensated clock signal to a selectable frequency for generating a counter output signal;

    flip-flop circuitry for splitting the counter output signal into first and second complementary square waves together forming a driver input signal, wherein a sample of at least one of the first and second complementary square waves is the divider reference signal; and

    a driver for amplifying the driver input signal for generating the driver output signal.

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