Multiple internal seal ring micro-electro-mechanical system vacuum packaging method

• US 7,396,478 B2
• Filed: 09/05/2007
• Issued: 07/08/2008
• Est. Priority Date: 06/10/2003
• Status: Active Grant

• Current Assignee: California Institute of Technology, The Boeing Co.
• Original Assignee: California Institute of Technology, The Boeing Co.
• Inventors: Peay, Chris S., Bae, Youngsam, Shcheglov, Kirill V., Challoner, A. Dorian, Hayworth, Ken J., Wiberg, Dean V., Yee, Karl Y.
• Primary Examiner(s): Ahmed; Shamim
• Application Number:
  US11/850,458
• Publication Number:
  US 20070298542A1
• Time in Patent Office: 307 Days
• Field of Search: 257/659, 257/660, 438/455, 438/456, 216/2, 216/41, 216/13
• US Class Current: 216/2
• CPC Class Codes: B81B 7/007 Interconnections between the MEMS and external electrical signals
• CPC Class Codes: G01C 19/5719 using planar vibrating masses driven in a translation vibration along an axis

Abstract

A Multiple Internal Seal Ring (MISR) Micro-Electro-Mechanical System (MEMS) vacuum packaging method that hermetically seals MEMS devices using MISR. The method bonds a capping plate having metal seal rings to a base plate having metal seal rings by wafer bonding the capping plate wafer to the base plate wafer. Bulk electrodes may be used to provide conductive paths between the seal rings on the base plate and the capping plate. All seals are made using only metal-to-metal seal rings deposited on the polished surfaces of the base plate and capping plate wafers. However, multiple electrical feed-through metal traces are provided by fabricating via holes through the capping plate for electrical connection from the outside of the package through the via-holes to the inside of the package. Each metal seal ring serves the dual purposes of hermetic sealing and providing the electrical feed-through metal trace.

Claims

1. A method of fabricating a device package, comprising:

(a) metal patterning of at least one seal ring on a base plate;

(b) etching of via holes in a capping plate;

(c) metal patterning of at least one seal ring on a bottom surface of the capping plate;

(d) aligning of the base plate and capping plate;

(e) bonding of the base plate and capping plate;

(f) electro-less plating of a thin metal layer on a top surface of the capping plate, including inside the via holes;

(g) electroplating of a thicker metal layer on top of the thin metal layer; and

(h) masking and etching of electrical trace patterns on the top surface of the capping plate.

2. The method of claim 1, further comprising etching of a cavity in the base plate.

3. The method of claim 1, wherein the aligning of the base plate and capping plate further comprises aligning of the seal rings of the base plate and capping plate.

4. The method of claim 1, wherein the bonding of the base plate and capping plate wafers uses heat and pressure in an evacuated chamber.

5. The method of claim 1, further comprising depositing of the solder bumps at one end of the electrical trace patterns etched on the top surface of the capping plate.

6. A method of fabricating a device package, comprising:

(a) metal patterning of at least one seal ring on a base plate;

(b) aligning of the base plate and a resonator plate;

(c) bonding of the base plate and resonator plate using heat and pressure in an evacuated chamber;

(d) etching of bulk electrodes on the resonator plate, wherein the doped silicon or a metalization of the resonator plate provides a conductive path for the electrodes;

(e) etching of at least one via hole in a capping plate;

(f) metal patterning of at least one seal ring on a bottom surface of the capping plate;

(g) aligning of the resonator plate and capping plate, and more specifically, the aligning of the bulk electrodes of the resonator plate with the seal rings of the capping plate;

(h) bonding of the of the resonator plate and capping plate using heat and pressure in an evacuated chamber.

(i) electro-less plating of a thin metal layer on a top surface of the capping plate including inside the via holes;

(j) electroplating of a thicker metal layer on the thin metal layer;

(k) masking and etching of an electrical trace pattern on the top surface of the capping plate.

7. The method of claim 6, wherein the bonding of the base plate and resonator plate uses heat and pressure in an evacuated chamber.

8. The method of claim 6, wherein doping or metalization of the resonator plate provides a conductive path for the bulk electrodes.

9. The method of claim 6, further comprising etching a cavity in the base plate.

10. The method of claim 6, wherein the aligning of the resonator plate and capping plate wafers comprises aligning of the bulk electrodes of the resonator plate with the seal rings of the capping plate.

11. The method of claim 6, wherein the bonding of the base plate and capping plate uses heat and pressure in an evacuated chamber.

12. The method of claim 6, further comprising depositing of the solder bumps at one end of the electrical trace pattern etched on the top surface of the capping plate.

13. The method of claim 6, further comprising using internal wire routing to reduce the number of bulk electrodes.

14. The method of claim 6, wherein the internal wire routing comprises criss-crossing wires and a plurality of metal routing layers.

15. The method of claim 6, wherein the crisscrossing wires use bridging bulk electrodes that act as vias between the base plate'"'"'s metal patterning and the capping plate'"'"'s internal metal pattern.