Semiconductor structure including silicide regions and method of making same

• US 7,396,767 B2
• Filed: 07/16/2004
• Issued: 07/08/2008
• Est. Priority Date: 07/16/2004
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lin, Cheng-Tung, Chang, Chih-Wei, Shue, Shau-Lin, Wu, Chii-Ming, Wang, Mei-Yun
• Primary Examiner(s): Geyer; Scott B.
• Application Number:
  US10/892,915
• Publication Number:
  US 20060011996A1
• Time in Patent Office: 1,453 Days
• Field of Search: 438/648, 438/649, 438/650, 438/651, 438/655, 438/656, 438/682, 438/683
• US Class Current: 438/682
• CPC Class Codes: H01L 21/28097 the final conductor layer next to the insulator being a metallic silicide
• CPC Class Codes: H01L 29/458 for thin film silicon, e.g. source or drain electrode
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66507 providing different silicide thicknesses on the gate and on source or drain

Abstract

A method of forming a silicided gate on a substrate having active regions, comprising the steps of: forming a first silicide in the active regions from a first material; and forming a second silicide in the gate from a second material, wherein the first silicide forms a barrier against the second material forming a silicide in the active regions during the second silicide forming step, wherein said second silicide is thicker than said first silicide.

Claims

1. A method of forming a silicided gate on a substrate having active regions, comprising the steps of:

forming a first silicide in the active regions from a first material; and

forming a second silicide in the gate from a second material, wherein said second material is deposited over said substrate and in contact with said gate and said first silicide, wherein said first silicide forms a barrier against said second material forming a silicide in said active regions during said second silicide forming step,

wherein said second silicide is thicker than said first silicide.

2. The method of claim 1,

wherein said first forming step comprises:

depositing said first material over said substrate and annealing to cause said first material to react with said active regions to form said first silicide; and

wherein said second forming step comprises;

depositing said second material over said substrate and annealing to cause said second material to react with said gate to form said second silicide, wherein said annealing of said second silicide forming step is performed at a temperature that substantially prevents said second material from reacting with said active regions.

3. The method of claim 1, further comprising the step of:

before said first silicide forming step, forming a shielding layer over said gate, whereby said shielding layer prevents said first material from reacting with the gate during said first silicide forming step.

4. The method of claim 3, wherein said shielding layer comprises SiN, SiON, SiC, SiCN or SiO₂.

5. The method of claim 3, further comprising the step of, after said first silicide forming step and before said second silicide forming step, removing said shielding layer over said gate.

6. The method of claim 5, wherein said removal step comprises etching said shielding layer with a solution comprising phosphoric acid.

7. The method of claim 1, wherein said second silicide forming step comprises fully siliciding said gate.

8. The method of claim 1, wherein said first silicide comprises a lowest resistivity phase of said first material and said second silicide comprises a lowest resistivity phase of said second material.

9. The method of claim 8, wherein said first and second materials comprise different materials.

10. A method of forming a silicided gate on a substrate having active regions, comprising the steps of:

(a) forming a shielding layer over said gate;

(b) after said forming step, depositing a first metal over said substrate;

(c) annealing to cause the first metal to react with the active regions to form a first silicide therein, whereby said shielding layer prevents said first metal from reacting with the gate during said annealing step;

(d) removing said shielding layer over said gate;

(e) depositing a second metal over said substrate in contact with said gate and said first silicide; and

(f) annealing at a temperature at or below about an annealing temperature of step (c) to cause the second metal to react with the gate to form a second silicide in said gate,

wherein said first silicide forms a baffler against said second metal forming a silicide in said active regions during step (f), and

wherein said second silicide is formed to a thickness greater than said first silicide.

11. The method of claim 10, wherein said first silicide comprises a lowest resistivity phase of said first metal and said second silicide comprises a lowest resistivity phase of said second metal.

12. The method of claim 11, wherein said first and second metals comprise different materials.

13. The method of claim 12, wherein said first silicide comprises CoSi₂ and said second silicide comprises NiSi.

14. The method of claim 10, wherein said shielding layer comprises SiN, SiON, SiC, SiCN or SiO₂.

15. The method of claim 10, wherein said gate is fully silicided.

16. A method of forming a silicided gate on a substrate having active regions, comprising the steps of:

forming a first silicide in the active regions from a first material, said forming step comprising depositing said first material over said substrate and annealing to cause said first material to react with said active regions to form said first silicide; and

forming a second silicide in the gate from a second material, said second silicide forming step comprising depositing said second material over said substrate and annealing to cause said second material to react with said gate to form said second silicide, wherein said annealing of said second silicide forming step is performed at a temperature that substantially prevents said second material from reacting with said active regions,

wherein said first silicide forms a barrier against said second material forming a silicide in said active regions during said second silicide forming step,

wherein said second silicide is thicker than said first silicide,

wherein said first material comprises cobalt and said second material comprises nickel.

17. The method of claim 16, wherein said temperature of said second silicide forming step is less than or equal to a temperature of said annealing of said first silicide forming step.

18. The method of claim 16, wherein said annealing of said first silicide forming step comprises an annealing at a temperature of at least about 650°

C., wherein said first silicide comprises CoSi₂.

19. The method of claim 18, wherein said annealing of said second silicide forming step comprises an annealing at a temperature between about 250-700°

C., wherein said second silicide comprises NiSi.

20. The method of claim 19, wherein said annealing of said second silicide forming step comprises annealing at a temperature between about 200-500°

C.

21. A method of forming a silicided gate on a substrate having active regions, comprising the steps of:

forming a first silicide in the active regions from a first material; and

forming a second silicide in the gate from a second material, wherein said first silicide forms a barrier against said second material forming a silicide in said active regions during said second silicide forming step,

wherein said second silicide is thicker than said first silicide,

wherein said second silicide forming step comprises fully siliciding said gate.

22. A method of forming a silicided gate on a substrate having active regions, comprising the step of:

depositing a first material over said substrate;

performing a first annealing of said substrate to cause the first material to react with the active regions to form a first silicide therein, wherein said gate is protected from silicidation during said annealing step;

depositing a second material over said substrate in contact with said gate and said first silicide; and

performing a second annealing of said substrate under processing conditions sufficient to cause the second material to react with the gate to form a second silicide in said gate but insufficient to cause further silicidation in said active area,

wherein said second silicide is formed to a thickness greater than said first silicide.

23. The method of claim 22, wherein a processing temperature of said second annealing is less than or equal to a processing temperature of said first annealing.

24. The method of claim 23, wherein said first material comprises cobalt and said second material comprises nickel.

25. The method of claim 24,

wherein said first annealing is at a temperature of at least about 650°

C., wherein said first silicide comprises CoSi₂,

wherein said second annealing is at a temperature between about 250-700°

C., wherein said second silicide comprises NiSi.

26. The method of claim 25, wherein said second annealing is at a temperature between about 200-500°

C.

27. The method of claim 22, wherein the gate is fully silicided.

28. The method of claim 22, wherein said first and second materials comprise different materials.

29. The method of claim 22, wherein at least one processing condition selected from the group consisting of processing temperature and processing time associated with the first annealing are different than for the second annealing.

30. The method of claim 22, wherein a processing temperature of said second annealing is less than a processing temperature of said first annealing.