Top layers of metal for high performance IC's

• US 7,397,135 B2
• Filed: 08/16/2007
• Issued: 07/08/2008
• Est. Priority Date: 12/21/1998
• Status: Expired due to Fees

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Mou-Shiung Lin
• Inventors: Lin, Mou-Shiung
• Primary Examiner(s): Pham; Long
• Application Number:
  US11/839,559
• Publication Number:
  US 20070273039A1
• Time in Patent Office: 327 Days
• Field of Search: 257/778, 257/691, 257/692, 257/758, 257/759, 257/760
• US Class Current: 257/778
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 21/76804 by forming tapered via holes
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 2224/02 Bonding areas; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/02311 Additive methods
• CPC Class Codes: H01L 2224/02313 Subtractive methods
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05184 Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05671 Chromium [Cr] as principal constituent
• CPC Class Codes: H01L 2224/05684 Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/1148 Permanent masks, i.e. masks left in the finished device, e.g. passivation layers
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/5222 : Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 23/5223 : Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5225 : Shielding layers formed together with wiring layers
• CPC Class Codes: H01L 23/5227 : Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/5228 : Resistive arrangements or effects of, or between, wiring layers other resistive arrangements H01L23/647
• CPC Class Codes: H01L 23/525 : with adaptable interconnections
• CPC Class Codes: H01L 23/5283 : Cross-sectional geometry
• CPC Class Codes: H01L 23/5286 : Arrangements of power or ground buses
• CPC Class Codes: H01L 23/5329 : Insulating materials
• CPC Class Codes: H01L 23/53295 : Stacked insulating layers
• CPC Class Codes: H01L 23/60 : Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 24/02 : Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/12 : Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 27/0676 : comprising combinations of diodes, or capacitors or resistors
• CPC Class Codes: H01L 27/08 : including only semiconductor components of a single kind
• CPC Class Codes: H01L 28/10 : Inductors
• CPC Class Codes: H01L 28/20 : Resistors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01018 : Argon [Ar]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15174 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15184 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15192 : Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H01L 2924/351 : Thermal stress
• CPC Class Codes: Y10T 428/12542 : More than one such component
• CPC Class Codes: Y10T 428/12993 : Surface feature [e.g., rough, mirror]

Abstract

A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

Claims

1. A semiconductor chip comprising:

a silicon substrate;

multiple transistors on said silicon substrate;

a first metallization structure over said silicon substrate, wherein said first metallization structure comprises a first metal layer over said silicon substrate, a second metal layer over said silicon substrate, a first metal interconnect over said silicon substrate, a second metal interconnect over said silicon substrate, a third metal interconnect over said silicon substrate and between said first and second metal interconnects, and a fourth metal interconnect over said silicon substrate and between said third and second metal interconnects, wherein said first, second, third and fourth metal interconnects are separated from one another by an insulating material, and wherein said first metallization structure comprises electroplated copper;

a dielectric layer between said first and second metal layers;

a passivation layer over said first metallization structure, over said dielectric layer and on said third and fourth metal interconnects, wherein said first, second, third and fourth metal interconnects are provided by a topmost metal layer under said passivation layer, and wherein said passivation layer comprises a topmost nitride layer of said semiconductor chip;

a polymer layer on said passivation layer and over said third and fourth metal interconnects, wherein said polymer layer has a thickness between 2 and 30 micrometers, greater than that of said passivation layer and greater than that of said dielectric layer, and wherein a first opening through said passivation layer and through said polymer layer is over a first contact point of said first metal interconnect and exposes said first contact point, and a second opening through paid passivation layer and through said polymer layer is over a second contact point of said second metal interconnect and exposes said second contact point; and

a second metallization structure on said polymer layer, over said passivation layer, over said third and fourth metal interconnects and over said first and second contact points, wherein said third and fourth metal interconnects are directly under said second metallization structure and are not connected to said second metallization structure through any opening through said polymer layer under said second metallization structure, wherein said first contact point is connected to said second contact point through said second metallization structure, wherein said second metallization structure comprises electroplated copper in said first and second openings and over said polymer layer, and wherein said second metallization structure comprises a third metal layer, on said polymer layer, having a thickness greater than that of said first metal layer and greater than that of said second metal layer.

2. The semiconductor chip of claim 1, wherein said polymer layer comprises polyimide.

3. The semiconductor chip of claim 1, wherein said polymer layer comprises benzocyclobutene (BCB).

4. The semiconductor chip of claim 1, wherein said passivation layer further comprises a topmost oxide layer of said semiconductor chip, wherein said topmost nitride layer of said semiconductor chip is over said topmost oxide layer of said semiconductor chip.

5. The semiconductor chip of claim 1, wherein said second metallization structure comprises a signal interconnect connecting said first contact point to said second contact point.

6. The semiconductor chip of claim 1, wherein said second metallization structure comprises a power interconnect connecting said first contact point to said second contact point.

7. The semiconductor chip of claim 1, wherein said second metallization structure comprises a ground interconnect connecting said first contact point to said second contact point.

8. The semiconductor chip of claim 1, wherein said second metallization structure has an entire top surface exposed to an ambience.

9. A semiconductor chip comprising:

a silicon substrate;

multiple transistors on said silicon substrate;

a first metallization structure over said silicon substrate, wherein said first metallization structure comprises a first metal layer over said silicon substrate, a second metal layer over said silicon substrate, a first metal interconnect over said silicon substrate, a second metal interconnect over said silicon substrate, and a third metal interconnect over said silicon substrate and between said first and second metal interconnects, wherein said first, second and third metal interconnects are separated from one another by an insulating material, and wherein said first metallization structure comprises electroplated copper;

a dielectric layer between said first and second metal layers;

a passivation layer over said first metallization structure, over said dielectric layer and on said third metal interconnect, wherein said first, second and third metal interconnects are provided by a topmost metal layer under said passivation layer, and wherein said passivation layer comprises a topmost nitride layer of said semiconductor chip;

a polymer layer on said passivation layer and over said third metal interconnect, wherein said polymer layer has a thickness between 2 and 30 micrometers, greater than that of said passivation layer and greater than that of said dielectric layer, and wherein a first opening through said passivation layer and through said polymer layer is over a first contact point of said first metal interconnect and exposes said first contact point, and a second opening through said passivation layer and through said polymer layer is over a second contact point of said second metal interconnect and exposes said second contact point; and

a second metallization structure on said polymer layer, over said passivation layer, over said third metal interconnect and over said first and second contact points, wherein said third metal interconnect is directly under said second metallization structure and is not connected to said second metallization structure through any opening through said polymer layer under said second metallization structure, wherein said first contact point is connected to said second contact point through said second metallization structure, wherein said second metallization structure comprises electroplated copper in said first and second openings and over said polymer layer, and wherein said second metallization structure comprises a third metal layer, on said polymer layer, having a thickness greater than that of said first metal layer and greater than that of said second metal layer.

10. The semiconductor chip of claim 9, wherein said polymer layer comprises polyimide.

11. The semiconductor chip of claim 9, wherein said polymer layer comprises benzocyclobutene (BCB).

12. The semiconductor chip of claim 9, wherein said passivation layer further comprises a topmost oxide layer of said semiconductor chip, wherein said topmost nitride layer of said semiconductor chip is over said topmost oxide layer of said semiconductor chip.

13. The semiconductor chip of claim 9, wherein said second metallization structure comprises a signal interconnect connecting said first contact point to said second contact point.

14. The semiconductor chip of claim 9, wherein said second metallization structure comprises a power interconnect connecting said first contact point to said second contact point.

15. The semiconductor chip of claim 9, wherein said second metallization structure comprises a ground interconnect connecting said first contact point to said second contact point.

16. The semiconductor chip of claim 9, wherein said second metallization structure has an entire top surface exposed to an ambience.

17. A semiconductor chip comprising:

a silicon substrate;

multiple transistors on said silicon substrate;

a first metallization structure over said silicon substrate, wherein said first metallization structure comprises a first metal layer over said silicon substrate, a second metal layer over said silicon substrate, a first metal interconnect over said silicon substrate and a second metal interconnect over said silicon substrate, wherein said first and second metal interconnects are separated from each other by an insulating material, and wherein said first metallization structure comprises electroplated copper;

a dielectric layer between said first and second metal layers;

a passivation layer over said first metallization structure and over said dielectric layer, wherein said first and second metal interconnects are provided by a topmost metal layer under said passivation layer, and wherein said passivation layer comprises a topmost nitride layer of said semiconductor chip;

a polymer layer on said passivation layer, wherein said polymer layer has a thickness between 2 and 30 micrometers, greater than that of said passivation layer and greater than that of said dielectric layer, and wherein a first opening through said passivation layer and through said polymer layer is over a first contact point of said first metal interconnect and exposes said first contact point, and a second opening through said passivation layer and through said polymer layer is over a second contact point of said second metal interconnect and exposes said second contact point; and

a second metallization structure on said polymer layer, over said passivation layers and over said first and second contact points, wherein said first contact point is connected to said second contact point though said second metallization structure, wherein said second metallization structure comprises electroplated copper in said first and second openings and over said polymer layer, and wherein said second metallization structure comprises a third metal layer, on said polymer layer, having a thickness greater than that of said first metal layer and greater than that of said second metal layer.

18. The semiconductor chip of claim 17, wherein said polymer layer comprises polyimide.

19. The semiconductor chip of claim 17, wherein said polymer layer comprises benzocyclobutene (BCB).

20. The semiconductor chip of claim 17, wherein said passivation layer further comprises a topmost oxide layer of said semiconductor chip, wherein said topmost nitride layer of said semiconductor chip is over said topmost oxide layer of said semiconductor chip.

21. The semiconductor chip of claim 17, wherein said second metallization structure comprises a power interconnect connecting said first contact point to said second contact point.

22. The semiconductor chip of claim 17 wherein said second metallization structure comprises a ground interconnect connecting said first contact point to said second contact point.

23. The semiconductor chip of claim 17, wherein said second metallization structure comprises a signal interconnect connecting said first contact point to said second contact point.

24. The semiconductor chip of claim 17, wherein said second metallization structure has an entire top surface exposed to an ambience.