Level shifter circuit

• US 7,397,297 B2
• Filed: 02/01/2007
• Issued: 07/08/2008
• Est. Priority Date: 02/02/2006
• Status: Expired due to Fees

• Current Assignee: North Star Innovations Inc. (Wi-LAN Inc.)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Kimura, Hiroyuki
• Primary Examiner(s): Wells, Kenneth B.
• Assistant Examiner(s): Jager, Ryan C
• Application Number:
  US11/670,398
• Publication Number:
  US 20070176668A1
• Time in Patent Office: 523 Days
• Field of Search: 327/333, 326/81
• US Class Current: 327/333
• CPC Class Codes: H03K 19/018521 of complementary type, e.g. CMOS

Abstract

A level shifter circuit, which includes a Schmitt trigger function, shifts voltage of a high level signal into a low voltage and shifts a signal at an intermediate value of an input voltage. The level shifter circuit includes an input terminal connected to low and high voltage circuits. The low voltage circuit outputs a low drive voltage or ground voltage. The high voltage circuit outputs a high drive voltage or a high reference voltage, which is supplied to an RS latch circuit via a potential adjustment circuit at a level equal to an output potential at the low voltage circuit. The RS latch circuit uses the output of the potential adjustment circuit when the input voltage shifts to a high level and uses the output of the low voltage circuit when the input voltage shifts to a low level.

Claims

1. A level shifter circuit comprising:

a low voltage circuit for performing a switching operation in accordance with a first switching voltage, which changes in relation with an input voltage applied to an input terminal, to output voltage between a low drive voltage and a low reference voltage, which is lower than the low drive voltage;

a high voltage circuit for performing a switching operation based on a second switching voltage, which is higher than the first switching voltage and changes in relation with the input voltage, to output voltage between a high drive voltage and a high reference voltage, which is lower than the high drive voltage;

a potential adjustment circuit for shifting an output of the high voltage circuit from the high drive voltage to the low drive voltage and from the high reference voltage to the low reference voltage; and

an output selection circuit for outputting a signal in accordance with an output of the potential adjustment circuit when a signal at the input terminal shifts from a low level to a high level, and for outputting a signal in accordance with an output of the low voltage circuit when the signal at the input terminal shifts from a high level to a low level.

2. The level shifter circuit according to claim 1, wherein:

the high reference voltage is such that the difference between the low drive voltage and the low reference voltage is substantially equal to the difference between the high drive voltage and the high reference voltage; and

the potential adjustment circuit lowers the voltage output from the high voltage circuit by a predetermined potential to shift the high drive voltage to the low drive voltage and the high reference voltage to the low reference voltage.

3. The level shifter circuit according to claim 1, wherein:

the low voltage circuit includes;

a first voltage adjustment means for adjusting the first switching voltage in relation with the input voltage; and

a complementary transistor circuit for performing a switching operation between the low drive voltage and the low reference voltage using an output of the first voltage adjustment means; and

the high voltage circuit includes;

a second voltage adjustment means for adjusting the second switching voltage in relation with the input voltage; and

a complementary transistor circuit for performing a switching operation between the high drive voltage and the high reference voltage using an output of the second voltage adjustment means.

4. The level shifter circuit according to claim 3, wherein:

a voltage between the low reference voltage and the high drive voltage is used as the input voltage;

the first voltage adjustment means includes an n channel MOS transistor having a gate terminal supplied with a second low drive voltage, which is higher than the low drive voltage by a threshold voltage;

the second voltage adjustment means includes a p-channel MOS transistor having a gate terminal supplied with a second high reference voltage, which is lower than the high reference voltage by a threshold voltage;

the complementary transistor circuit of the low voltage circuit is supplied with the second low drive voltage via a third voltage adjustment means including an n-channel lAOS transistor; and

the complementary transistor circuit of the high voltage circuit is supplied with the second high reference voltage via a fourth voltage adjustment means including a p-channel lAOS transistor.

5. The level shifter circuit according to claim 1, wherein:

the output selection circuit includes an RS circuit having an input terminal connected to an output terminal of the potential adjustment circuit and an output terminal of the low voltage circuit.