CMOS sensor with over-saturation abatement

• US 7,397,505 B2
• Filed: 01/17/2002
• Issued: 07/08/2008
• Est. Priority Date: 01/17/2002
• Status: Expired due to Term

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Zoran Corporation (Qualcomm, Inc.)
• Inventors: Harris, Brannon, Brehmer, Kevin E.
• Primary Examiner(s): Vu; Ngoc-Yen T.
• Assistant Examiner(s): Quiett; Carramah J
• Application Number:
  US10/053,111
• Publication Number:
  US 20030133627A1
• Time in Patent Office: 2,364 Days
• Field of Search: 348/241, 348/243, 348301-302, 348307-310
• US Class Current: 348/243
• CPC Class Codes: H04N 23/76 by influencing the image signals
• CPC Class Codes: H04N 25/616 involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array

Abstract

A method and apparatus are described that detect and correct for over-saturation lighting conditions in a CMOS Image Sensor.

Claims

1. A method for image sensing comprising the acts of:

producing, from a photo detector, a plurality of detected electronic signals responsive to an optical image;

amplifying, with a column buffer amplifier, signals selected from the detected electronic signals to produce a plurality of amplified signals;

sampling, with a correlated double sampler, signals selected from the amplified signals to produce a plurality of sampled signals; and

clamping, by a clamp circuit, at least one signal selected from the sampled signals during a reset phase of the correlated double sampler in response to a detecting of at least one over-saturation condition, whereby image inversion is at least partially abated.

2. The method of claim 1 wherein

the photo detector comprises a photo diode.

3. The method of claim 1 wherein

the photo detector comprises a photo gate.

4. The method of claim 1 wherein the clamp circuit is implemented in a technology selected from a list consisting of N-well CMOS process technology and of P-well CMOS process technology.

5. The method of claim 1, wherein the clamp circuit limits a reset voltage.

6. In an image sensor that correlates a reset sample of a first signal during a first interval after reset of a photo detector for a pixel and a second sample of the first signal during a later interval in the same sampling cycle as the first interval to produce a luminance signal for said pixel, a method comprising:

detecting that the first signal is slewing excessively rapidly during the first interval; and

in response to said detecting, limiting the value of the reset sample;

whereby the image sensor produces an output of improved accuracy by abating an error in the luminance signal for said pixel due to said excessively rapid slewing, wherein the error is an image inversion due to over-saturation.

7. The method of claim 6 wherein:

the detecting is responsive to the first signal reaching the bounds of a predetermined threshold.

8. A method of image sensing, comprising:

determining a reset sample of a first signal during a first interval after reset of a pixel in a photo detector;

determining a second sample of the first signal during a later interval in the same sampling cycle as the first interval;

correlating the reset sample and the second sample to produce a luminance signal for said pixel;

detecting that the first signal is slewing excessively rapidly during the first interval; and

in response to said detecting, limiting the value of the reset sample, whereby image inversion is at least partially abated.