Multi-bit-per-cell flash EEPROM memory with refresh
First Claim
1. A non-volatile semiconductor memory comprising:
- an array of memory cells;
drivers and decoders coupled to apply voltages to the array to read any memory cell in the array, wherein each memory cell that stores data has a threshold voltage corresponding to a range of threshold values that identifies a multibit data value written in the memory cell, wherein the ranges of threshold values that identify data values are separated from each other by at least one range of threshold values corresponding to errors in the threshold voltages of memory cells storing data;
an error detection circuit that detects errors in threshold voltages of memory cells storing data, wherein in response to detecting an error in the threshold voltage of a memory cell, the error detection circuit signals for a refresh operation;
a control circuit coupled to control the drivers and decoders, wherein during the refresh operation, the control circuit writes a corrected threshold voltage that corrects the error that the error detection circuit detected.
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Abstract
A multibit-per-cell non-volatile memory divides the suitable threshold voltages of memory cells into ranges corresponding to allowed states for storage of data and ranges corresponding to forbidden zones indicating a data error. A read process checks whether a threshold voltage is in a forbidden zone. Alternately, a refresh process includes reprogramming the threshold voltage into an allowed state. In the case of a flash memory, a refresh reads a sector of the memory and saves corrected data from the sector in a buffer or another sector. The corrected data from the buffer or other sector can be written back in the original sector, or the corrected data can be left in the other sector with addresses of the original sector being mapped to the other sector. Refresh process for the non-volatile memory can be performed in response to detecting a threshold voltage in a forbidden zone or periodically.
173 Citations
12 Claims
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1. A non-volatile semiconductor memory comprising:
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an array of memory cells; drivers and decoders coupled to apply voltages to the array to read any memory cell in the array, wherein each memory cell that stores data has a threshold voltage corresponding to a range of threshold values that identifies a multibit data value written in the memory cell, wherein the ranges of threshold values that identify data values are separated from each other by at least one range of threshold values corresponding to errors in the threshold voltages of memory cells storing data; an error detection circuit that detects errors in threshold voltages of memory cells storing data, wherein in response to detecting an error in the threshold voltage of a memory cell, the error detection circuit signals for a refresh operation; a control circuit coupled to control the drivers and decoders, wherein during the refresh operation, the control circuit writes a corrected threshold voltage that corrects the error that the error detection circuit detected. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A non-volatile semiconductor memory comprising:
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an array of memory cells; drivers and decoders coupled to apply voltages to the array to read any memory cell in the array, wherein each memory cell that stores data has a threshold voltage that identifies a multibit data value written in the memory cell; and a reference generator that generates signals indicate bounds of a plurality of ranges of threshold voltages allowed for the memory cells that store data, wherein each range in the plurality corresponds to a multibit value that differs in only a single bit from a multibit value corresponding to a range that is adjacent in threshold voltage, and wherein the reference generator further generates reference signals indicating bounds of one or more forbidden ranges of threshold voltages corresponding to data errors, wherein the allowed ranges of threshold voltages are separated from each other by at least one forbidden range. - View Dependent Claims (11, 12)
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Specification