Compressed event counting technique and application to a flash memory system

• US 7,397,707 B2
• Filed: 08/30/2006
• Issued: 07/08/2008
• Est. Priority Date: 09/14/2000
• Status: Expired due to Term

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Mokhlesi, Nima
• Primary Examiner(s): Lam; David
• Application Number:
  US11/468,661
• Publication Number:
  US 20070070692A1
• Time in Patent Office: 678 Days
• Field of Search: 365/185.33, 365/236, 365/189.07, 711/100, 711104-105, 711162-163, 711217-219
• US Class Current: 365/185.33
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically

Abstract

A non-volatile flash memory system counts the occurrences of an event, such as the number of times that individual blocks have been erased and rewritten, by updating a compressed count only once for the occurrence of a large number of such events. Complementary embodiments include updating the compressed count based upon a random number or upon the actual count matching a multiple of the fixed number. These techniques also have application to monitoring other types of recurring events in flash memory systems or in other types of electronic systems. In another aspect of the present invention, provisions are made to maintain an accurate experience count if the memory system experiences an improper shutdown, for example in case of power loss or removal of a memory card.

Claims

1. A method of maintaining a compressed count of a number of occurrences of an event that recurs during operation of an electronic system, comprising:

generating a number in response to the individual occurrences of the event,

determining when the incremented count matches a multiple of a first predetermined value, and

in response to the generated number matching a multiple of said first predetermined value, updating a compressed count of the number of occurrences of the event within the system, wherein the compressed count is maintained in non-volatile memory.

2. The method of claim 1, wherein generating a number comprises either incrementing or decrementing of a count.

3. The method of claim 2, wherein the incremented or decremented count is maintained in volatile memory.

4. The method of claim 3, wherein the system comprises a controller including a micro-processor that controls programming of data into addressed blocks of memory cells in the non-volatile memory, reading data from addressed blocks of memory cells and erasing data from one or more of addressed blocks of memory cells at a time, and wherein the volatile memory is part of the controller.

5. The method of claim 1, wherein the non-volatile memory is a flash memory.

6. The method of claim 1, wherein the recurring event includes erasure of an addressed portion of the non-volatile memory.

7. The method of claim 1, wherein generating a number comprises generating a random or pseudo-random number and the multiple of the first predetermined value is the first predetermined value itself.

8. The method of claim 7, wherein the first predetermined value is one of N distinct values of random numbers that are possible to be generated, a maximum number M of events are permitted to occur in the electronic system, and the compressed count is maintained up to at least a number equal to M divided by N.

9. The method of claim 7, additionally comprising seeding a first random number generator upon initialization of the electronic system with a number generated by a second random number generator.

10. The method of claim 7, wherein determining when the generated random number matches said at predetermined value takes into account the number of said events that have cumulatively occurred in order to decrease a probability that the match will occur for an individual generated random number as the cumulative number of said events increases.

11. The method of claim 7, wherein both generating the random number and determining when the random number equals the first predetermined value occur during an individual erase voltage pulse applied to an addressed portion of the non-volatile memory.

12. A non-volatile memory system, comprising:

a plurality of blocks of non-volatile memory cells wherein the cells within individual ones of the blocks are simultaneously erasable,

control circuitry, including a micro-processor, that controls programming of data into addressed blocks of memory cells, reading data from addressed blocks of memory cells and erasing data from one or more of addressed blocks of memory cells at a time,

storage, provided within the plurality of blocks of memory cells, that maintains first counts associated with corresponding individual ones of the memory cell blocks,

number generation circuitry that generates a number in response to a corresponding addressed block being erased, and

a comparator connected to receive and compare the generated number with a first predetermined value,

wherein, in response to the generated number matching a multiple of the first predetermined value, the memory system updates the first count associated with the corresponding addressed block being erased.

13. The non-volatile memory system of claim 12, wherein said controller comprises the number generation circuitry and the comparator.

14. The memory system of claim 12, wherein the number generator is a counter that increments or decrements a second count in response to said corresponding addressed block being erased.

15. The non-volatile memory system of claim 14, wherein the second count is maintained in volatile memory.

16. The non-volatile memory system of claim 15, wherein said controller comprises said volatile memory.

17. The non-volatile memory system of claim 15, further comprising:

a reserve power source, wherein, in response to an improper shut-down indication, the controller updates the first count based on the incremented value of the second count using said reserve power source.

18. The memory system of claim 12, wherein the number generator is a random or pseudo-random number generator and the multiple of the first predetermined value is the first predetermined value itself.

19. The memory system of claim 18, wherein the number generator is characterized by generating one of a controlled total number of possible different random numbers, and wherein said total number of possible different random numbers is controlled by said first counts.

20. The memory system of claim 12, wherein said plurality of blocks of non-volatile memory cells form a flash memory.