Compressed event counting technique and application to a flash memory system
First Claim
1. A method of maintaining a compressed count of a number of occurrences of an event that recurs during operation of an electronic system, comprising:
- generating a number in response to the individual occurrences of the event,determining when the incremented count matches a multiple of a first predetermined value, andin response to the generated number matching a multiple of said first predetermined value, updating a compressed count of the number of occurrences of the event within the system, wherein the compressed count is maintained in non-volatile memory.
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Abstract
A non-volatile flash memory system counts the occurrences of an event, such as the number of times that individual blocks have been erased and rewritten, by updating a compressed count only once for the occurrence of a large number of such events. Complementary embodiments include updating the compressed count based upon a random number or upon the actual count matching a multiple of the fixed number. These techniques also have application to monitoring other types of recurring events in flash memory systems or in other types of electronic systems. In another aspect of the present invention, provisions are made to maintain an accurate experience count if the memory system experiences an improper shutdown, for example in case of power loss or removal of a memory card.
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Citations
20 Claims
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1. A method of maintaining a compressed count of a number of occurrences of an event that recurs during operation of an electronic system, comprising:
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generating a number in response to the individual occurrences of the event, determining when the incremented count matches a multiple of a first predetermined value, and in response to the generated number matching a multiple of said first predetermined value, updating a compressed count of the number of occurrences of the event within the system, wherein the compressed count is maintained in non-volatile memory. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A non-volatile memory system, comprising:
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a plurality of blocks of non-volatile memory cells wherein the cells within individual ones of the blocks are simultaneously erasable, control circuitry, including a micro-processor, that controls programming of data into addressed blocks of memory cells, reading data from addressed blocks of memory cells and erasing data from one or more of addressed blocks of memory cells at a time, storage, provided within the plurality of blocks of memory cells, that maintains first counts associated with corresponding individual ones of the memory cell blocks, number generation circuitry that generates a number in response to a corresponding addressed block being erased, and a comparator connected to receive and compare the generated number with a first predetermined value, wherein, in response to the generated number matching a multiple of the first predetermined value, the memory system updates the first count associated with the corresponding addressed block being erased. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20)
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Specification