Distributed write data drivers for burst access memories

• US 7,397,711 B2
• Filed: 05/18/2006
• Issued: 07/08/2008
• Est. Priority Date: 12/23/1994
• Status: Expired due to Fees

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Manning, Troy A., Merritt, Todd A.
• Primary Examiner(s): Nguyen; Viet Q
• Application Number:
  US11/419,166
• Publication Number:
  US 20060198180A1
• Time in Patent Office: 782 Days
• Field of Search: 365/189.16, 365/189.05, 365/189.08, 365/236, 365/230.06
• US Class Current: 365/189.16
• CPC Class Codes: G06F 12/0638 Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G11C 11/407 for memory cells of the field-effect type
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 7/1021 Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address
• CPC Class Codes: G11C 7/1024 Extended data output [EDO] mode, i.e. keeping output buffer enabled during an extended period of time
• CPC Class Codes: G11C 7/1027 Static column decode serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled bit line addresses
• CPC Class Codes: G11C 7/1039 using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: G11C 7/1048 Data bus control circuits, e.g. precharging, presetting, equalising
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/109 Control signal input circuits
• CPC Class Codes: G11C 7/1096 Write circuits, e.g. I/O line write drivers
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management

Abstract

An address strobe latches a first address. A burst cycle increments the address internally with additional address strobes. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating toggling Read/Write control line at cycle frequency. Control line transition terminates access and initializes another burst access. Write cycle times are maximized thereby allowing increases in burst mode operating frequencies. Logic near sense amplifiers control write-data drivers thereby providing maximum write times without crossing current during I/O line equilibration. By gating global write-enable signals with global equilibrate signals locally at sense amps, local write-cycle control signals are provided and valid for essentially the entire cycle time minus an I/O line equilibration period in burst access memory. For nonburst mode, write begins following end of equilibration cycle to provide maximum write time without interfering with subsequent access-cycle address setup time.

Claims

1. A method of writing data into a memory device comprising:

asserting an equilibrate signal to an equilibration device to equilibrate internal data lines of the memory device in response to providing a memory address;

communicating the equilibrate signal to a plurality of a data driver enable circuits located in close proximity and coupled to write data drivers;

communicating a write enable signal to the plurality of data driver enable circuits;

deasserting the equilibrate signal after the internal data lines are equilibrated;

gating the write enable signal through at least one of the data driver enable circuits in response to deasserting the equilibrate signal;

driving data onto the internal data lines using the write data drivers in response to the gating; and

storing data in a memory cell in response to driving data.

2. The method of claim 1, wherein the recited steps are initiated in the recited order.

3. The method of claim 1, wherein the memory device is a burst extended data out dynamic random access memory device.

4. The method of claim 1, wherein gating the write enable signal through at least one of the data driver enable circuits in response to deasserting the equilibrate signal comprises:

routing the write enable signal to a data sense amplifier;

latching the write enable signal;

generating the equilibrate signal based on detection of an address transition; and

logically combining a version of the latched write enable signal and a version of the equilibrate signal.

5. The method of claim 4, wherein logically combining the version of the latched write enable signal and the version of the equilibrate signal comprises nanding the version of the latched write enable signal and the version of the equilibrate signal.

6. The method of claim 4, wherein gating occurs at the data sense amplifier.

7. The method of claim 1, wherein providing an address to the memory device comprises providing an address to a memory device including:

a memory array coupled to a column decoder and a row decoder,

a latch coupled to the row decoder;

an active-low row address strobe input coupled to the latch;

a plurality of at least 10 address inputs coupled to the latch;

a counter coupled between the plurality of address inputs and the column decoder; and

an active-low column address strobe input coupled to the counter.

8. The method of claim 1, wherein the memory comprises a memory organized according to a pipelined or prefetched architecture.

9. The method of claim 1, wherein the write enable signal is an active-low signal.

10. The method of claim 4, further comprising routing the equilibrate signal to the data sense amplifier.

11. The method of claim 1, wherein deasserting the write enable signal includes placing the write enable signal in an active low condition without a write enable delay.

12. The method of claim 1, further comprising latching and incrementing a column address signal after a first /CAS signal falling edge.

13. The method of claim 1, wherein driving data includes driving complementary data read lines.

14. The method of claim 1, wherein driving data includes driving data when enabled by a logical combination of the equilibrate signal and the write enable signal.