Flash EEprom system

• US 7,397,713 B2
• Filed: 01/21/2003
• Issued: 07/08/2008
• Est. Priority Date: 04/13/1989
• Status: Expired due to Fees

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Harari, Eliyahou, Mehrotra, Sanjay, Norman, Robert D.
• Primary Examiner(s): Nguyen; Viet Q
• Application Number:
  US10/348,739
• Publication Number:
  US 20030110411A1
• Time in Patent Office: 1,995 Days
• Field of Search: 365/200, 365/230.01, 365/230.06, 365/230.08
• US Class Current: 365/200
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0866 for peripheral storage systems, e.g. disk cache
• CPC Class Codes: G06F 12/0875 with dedicated cache, e.g. instruction or stack
• CPC Class Codes: G06F 12/123 with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G06F 2212/312 In storage controller
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 2212/7207 management of metadata or control data
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G06F 3/0601 Interfaces specially adapted for storage systems
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0652 Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket
• CPC Class Codes: G06F 3/0664 at device level, e.g. emulation of a storage device or system
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/068 : Hybrid storage device
• CPC Class Codes: G06F 3/0688 : Non-volatile semiconductor memory arrays
• CPC Class Codes: G11C 11/5621 : using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 : Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 : Erasing circuits
• CPC Class Codes: G11C 16/10 : Programming or data input circuits
• CPC Class Codes: G11C 16/16 : for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/3436 : Arrangements for verifying correct programming or erasure
• CPC Class Codes: G11C 16/344 : Arrangements for verifying correct erasure or for detecting overerased cells
• CPC Class Codes: G11C 16/3445 : Circuits or methods to verify correct erasure of nonvolatile memory cells
• CPC Class Codes: G11C 16/3454 : Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 16/3459 : Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2211/5621 : Multilevel programming verification
• CPC Class Codes: G11C 2211/5634 : Reference cells
• CPC Class Codes: G11C 2211/5643 : Multilevel memory comprising cache storage devices
• CPC Class Codes: G11C 2216/18 : Flash erasure of all the cells in an array, sector or block simultaneously
• CPC Class Codes: G11C 29/00 : Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
• CPC Class Codes: G11C 29/26 : Accessing multiple arrays G11C29/24 takes precedence
• CPC Class Codes: G11C 29/34 : Accessing multiple bits simultaneously
• CPC Class Codes: G11C 29/52 : Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: G11C 29/765 : in solid state disks
• CPC Class Codes: G11C 29/82 : for EEPROMs
• CPC Class Codes: G11C 7/1039 : using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
• CPC Class Codes: G11C 8/12 : Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

A system of Flash EEprom memory chips with controlling circuits serves as non-volatile memory such as that provided by magnetic disk drives. Improvements include selective multiple sector erase, in which any combinations of Flash sectors may be erased together. Selective sectors among the selected combination may also be de-selected during the erase operation. Another improvement is the ability to remap and replace defective cells with substitute cells. The remapping is performed automatically as soon as a defective cell is detected. When the number of defects in a Flash sector becomes large, the whole sector is remapped. Yet another improvement is the use of a write cache to reduce the number of writes to the Flash EEprom memory, thereby minimizing the stress to the device from undergoing too many write/erase cycling.

Claims

1. A storage device comprising:

a controller to carry out an interface with a host system, via a host bus, to receive instructions from said host system and to control operations to be performed within said storage device; and

a nonvolatile semiconductor flash memory coupled with said controller,

wherein said nonvolatile semiconductor flash memory is (i) electrically erasable and electrically programmable, (ii) includes a plurality of erase units in connection with an electrical erase operation, and (iii) is electrically programmable to store a sector data from said host system and to store address information for defect mapping,

wherein said controller includes an address register file, and is such as to allow a host logical address from said host system to be converted to a physical address of said nonvolatile semiconductor flash memory based on data stored in said address register file, and

wherein said data of said address register file is originated from said address information stored in said nonvolatile semiconductor flash memory by said controller at start of a system operation, and then said controller accesses said nonvolatile semiconductor flash memory based upon said data of said address register file.

2. A storage device according to claim 1, wherein each erase unit of said plurality of erase units is electrically programmable to store a corresponding address information.

3. A storage device according to claim 1, wherein said nonvolatile semiconductor flash memory is a flash memory chip.

4. A storage device according to claim 3, wherein each erase unit of said plurality of erase units is electrically programmable to store a corresponding address information.

5. A storage device comprising:

a controller to control operations to be performed within said storage device, wherein said controller includes a memory to store defect map data; and

a nonvolatile semiconductor flash memory coupled with said controller,

wherein said nonvolatile semiconductor flash memory is electrically erasable and electrically programmable, and includes a plurality of erase units in connection with an electrical erase operation, and

wherein said defect map data of said controller memory is originated from data stored in said nonvolatile semiconductor flash memory by said controller at start of an operation, and then said controller controls the operation of said nonvolatile semiconductor flash memory based upon said defect map data stored by said controller memory.

6. A storage device according to claim 5, wherein said nonvolatile semiconductor flash memory is a flash memory chip.

7. A storage device comprising:

a controller for carrying out an interface with a host system via a host bus, receiving instructions from said host system and controlling operations to be performed within said storage device; and

a non-volatile semiconductor flash memory coupled with said controller;

wherein said non-volatile semiconductor flash memory is electrically erasable and electrically programmable,

wherein said non-volatile semiconductor flash memory includes a plurality of erase units in connection with an electrical erase operation,

wherein said non-volatile semiconductor flash memory is electrically programmable to store a sector data from said host system and to store address information,

wherein said controller includes an address register file memory for storing defect mapping data, wherein a host logical address from said host system can be converted to a physical address of said non-volatile semiconductor flash memory based on data stored in said address register file memory, and

wherein said data of said address register file memory is originated from said address information stored in said non-volatile semiconductor flash memory by said controller at the start of an operation of said storage device, and then said controller accesses said non-volatile semiconductor flash memory based upon said data of said address register file memory.

8. A storage device in claim 7, wherein said non-volatile semiconductor flash memory is a flash memory chip.

9. A storage device in claim 7, wherein each erase unit of said plurality of erase units is electrically programmable and stores a corresponding address information.

10. A storage device in claim 8, wherein each erase unit of said plurality of erase units is electrically programmable and stores a corresponding address information.

11. A storage device comprising:

a controller for controlling operations to be performed within said storage device, wherein said controller includes a register file to store defect mapping data; and

a non-volatile semiconductor flash memory coupled with said controller;

wherein said non-volatile semiconductor flash memory is electrically erasable and electrically programmable,

wherein said non-volatile semiconductor flash memory includes a plurality of erase units in connection with an electrical erase operation, and

wherein said defect mapping data of said register file is originated from data stored in said non-volatile semiconductor flash memory by said controller at the start of an operation of said storage device, and then said controller controls the operation of said non-volatile semiconductor flash memory based upon said defect mapping data stored by said register file.

12. A storage device in claim 11, wherein said non-volatile semiconductor flash memory is a flash memory chip.

13. A storage device comprising:

a controller which carries out interface with a host system via a host bus, receives instructions from said host system and controls operations to be performed within said storage device;

an address table for defect mapping which receives a logical address of data in a data write operation from said host system, via said host bus, and converts said logical address to a physical address; and

a nonvolatile semiconductor flash memory coupled with said controller,

wherein said nonvolatile semiconductor flash memory is electrically erasable and electrically programmable and is divided into a plurality of physical sectors identified by physical addresses,

wherein said controller receives said physical address from said address table and writes said data in said data write operation from said host system via said host bus into one physical sector of said plurality of physical sectors,

wherein said address table is comprised of a volatile memory, the logical address from said host system can be converted to the physical address of said nonvolatile semiconductor flash memory based on data stored in said address table of said volatile memory,

wherein said data of said address table of said volatile memory is originated from an address information stored in said nonvolatile semiconductor flash memory by said controller at start of a system operation, and then said controller accesses said nonvolatile semiconductor flash memory based upon said data of said address table of said volatile memory, and

wherein said address table converts a logical address received in the write operation from said host system, via said host bus, to the physical address which is different from the physical address to which said address table converted a logical address, identical to the logical address to be presently converted, in a preceding write operation from said host system, via said host bus.

14. A storage device according to claim 13,

wherein said nonvolatile semiconductor flash memory includes a plurality of erase blocks in connection with an electrical erase operation, and

wherein a power supply is initiated at said start of system operation.

15. A storage device according to claim 14, wherein each erase block of said plurality of erase blocks is electrically programmable and is for storing a corresponding address information.

16. A storage device according to claim 15, wherein said controller is a one-chip microcomputer which includes a RAM core as said volatile memory for storing said data of said address table.

17. A storage device according to claim 14, wherein said controller is a one-chip microcomputer which includes a RAM core as said volatile memory for storing said data of said address table.

18. A storage device according to claim 13, wherein said nonvolatile semiconductor flash memory is a flash memory chip and includes a plurality of erase blocks in connection with an electrical erase operation.

19. A storage device according to claim 18, wherein each erase block of said plurality of erase blocks is electrically programmable and is for storing a corresponding address information.

20. A storage device according to claim 19, wherein said controller is a one-chip microcomputer which includes a RAM core as said volatile memory for storing said data of said address table.

21. A storage device according to claim 18,

wherein said controller is a one-chip microcomputer which includes a RAM core as said volatile memory for storing said data of said address table.

22. A storage device according to claim 13, wherein each erase block of said plurality of erase blocks is electrically programmable and is for storing a corresponding address information.

23. A storage device according to claim 22, wherein said controller is a one-chip microcomputer which includes a RAM core as said volatile memory for storing said data of said address table.

24. A storage device according to claim 13, wherein said controller is a one-chip microcomputer which includes a RAM core as said volatile memory for storing said data of said address table.