Loop filter with gear shift for improved fractional-N PLL settling time

• US 7,398,071 B2
• Filed: 12/17/2004
• Issued: 07/08/2008
• Est. Priority Date: 12/17/2004
• Status: Expired due to Fees

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Jensen, Henrik T.
• Primary Examiner(s): Phu; Sanh D.
• Application Number:
  US11/015,101
• Publication Number:
  US 20060135105A1
• Time in Patent Office: 1,299 Days
• Field of Search: 455/260, 455/161.2, 455/165.1, 455/139, 455/180.3, 331/16, 331/17
• US Class Current: 455/260
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H03L 7/1075 by changing characteristics of the loop filter, e.g. changing the gain, changing the bandwidth H03L7/1072 takes precedence
• CPC Class Codes: H03L 7/1976 using a phase accumulator for controlling the counter or frequency divider

Abstract

An integrated circuit radio frequency (RF) transmitter includes a phase locked loop having a multi-mode loop filter that is operable to provide wide band response with a fast settle time in a startup mode of operation and a relatively more narrow response with a longer settle time but with improved filtering in a steady state mode of operation according to one embodiment of the invention. The multi-mode loop filter includes, in one embodiment, selectable resistance circuitry for selecting between a plurality of resistance values based upon a two-state multi-mode control signal to provide the selected resistance values and selectable capacitance circuitry for selecting between a plurality of capacitance values based upon the two-state multi-mode control signal and for operatively coupling selected capacitors to selected resistors to provide the selected capacitance values. As a further aspect of the embodiment of the present invention, the multi-mode loop filter includes buffers for charging non-selected capacitors while not operationally coupled to the multi-mode loop filter to avoid additional settle time for the circuitry.

Claims

1. A phase locked loop (PLL), comprising:

a phase frequency detector operable to produce an error signal based upon a phase difference between a reference signal and a feedback signal;

a charge pump operable to produce an error current based upon the error signal;

a multi-mode loop filter operable to produce a control voltage based upon the error current;

an oscillator operable to produce an oscillation and the feedback signal in an undivided form based upon the control voltage;

selectable resistance circuitry of the multi-mode loop filter for selecting between a plurality of resistance values based upon a two-state multi-mode control signal to provide the selected resistance values;

selectable capacitance circuitry of the multi-mode loop filter for selecting between a plurality of capacitance values based upon the two-state multi-mode control signal and for operatively coupling selected capacitors to selected resistors to provide the selected capacitance values;

buffers for charging non-selected capacitors of the selectable capacitance circuitry while not operationally coupled to the multi-mode loop filter; and

wherein the two-state multi-mode control signal is operable to select between the plurality of resistance values and capacitance values to select between the startup mode and the steady state mode and wherein the multi-mode loop filter operates in a startup mode characterized by a wide-band response with a fast settle time and in a steady state mode characterized by narrow-band response with improved filtering.

2. The PLL of claim 1 wherein the multi-mode loop filter includes:

multi-value resistance logic operable to produce a first resistance value based upon a first state of a two-state multi-mode control signal and a second resistance value based upon a second state of the two-state multi-mode control signal;

multi-value capacitance logic operable to produce a first capacitance value based upon the first state of the two-state multi-mode control signal and a second capacitance value based upon the second state of the two-state multi-mode control signal; and

wherein selected capacitors provide one of the first and second capacitance values and selected resistors provide one of the first and second resistance values are operatively coupled to convert error current received from the charge pump to the control voltage.

3. The PLL of claim 2 wherein the multi-value capacitance logic further includes switching logic to selectively couple at least one buffer in series with at least one capacitor wherein, when coupled, is coupled between an input node of the multi-value capacitance logic and the at least one capacitor and wherein when not coupled, the at least one capacitor is coupled directly to the input node.

4. The PLL of claim 1 wherein the multi-mode loop filter includes multi-value capacitance logic that includes a plurality of capacitors coupled to receive a charge wherein, when the PLL is in a startup mode of operation, is operable to couple at least one buffer in series with at least one capacitor to enable the at least one capacitor to continue to charge while removing the at least one capacitor from operation of the PLL.

5. The PLL of claim 1 wherein the phase frequency detector produces a multi-state error signal further to drive the charge pump and further wherein the phase frequency detector produces a mode change enable signal to allow the multi-mode loop filter to change between the startup mode and the steady state mode once a specified time value has expired.

6. The PLL of claim 5 wherein the mode change enable signal is only set to an enable state when the error signal is in a state that does not result in the error current being produced to the multi-mode loop filter.

7. The PLL of claim 5 further including timing logic to produce a mode shift signal once a specified number of pulses have been received from a clock and once the mode change enable signal is set.

8. The PLL of claim 1 further including multi-modulus divider for dividing an oscillation by a selected value and further including a delta-sigma modulation control logic for selecting a divider ratio of the multi-modulus divider.

9. A method within a phase-locked loop (PLL), comprising:

producing an error signal based upon a phase difference between a reference signal and a feedback signal;

producing an error current based upon the error signal;

producing a control voltage based upon the error current;

producing an oscillation based upon the control voltage;

selecting between a plurality of resistance values in a multi-mode loop filter based upon a two-state multi-mode control signal to provide the selected resistance values;

selecting between a plurality of capacitance values based upon the two-state multi-mode control signal and operatively coupling selected capacitors to selected resistors to provide the selected capacitance values;

charging non-selected capacitors while not operationally coupled to the multi-mode loop filter; and

wherein selecting comprises selecting a first set of resistance values and capacitance values in a startup mode and selecting a second set of resistance values and capacitance values in a steady state mode of operation and operating in a startup mode characterized by a wide-band response with a fast settle time and then operating in a steady state mode characterized by narrow-band response with improved filtering.

10. The method of claim 9 further including:

producing a first resistance value based upon a first state of a two-state multi-mode control signal and producing a second resistance value based upon a second state of the two-state multi-mode control signal;

producing a first capacitance value based upon the first state of the two-state multi-mode control signal and producing a second capacitance value based upon the second state of the two-state multi-mode control signal; and

converting error current received from the charge pump to the control voltage.

11. The method of claim 10 further including selectively coupling at least one buffer in series with at least one capacitor to charge the at least one capacitor while the at least one capacitor is not operatively coupled to provide filtering.

12. The method of claim 9 further including determining that a specified amount of time has passed and that the loop filter should be changed from a start up mode to a steady state mode of operation.

13. The method of claim 12 further including producing a multi-state error signal to drive the charge pump and further producing a mode change enable signal to allow the multi-mode loop filter to change between the startup mode and the steady state mode once the specified time value has passed.

14. The method of claim 13 further including setting the mode change enable signal to an enable state only when the error signal is in a state that does not result in the error current being produced to the multi-mode loop filter.

15. The method of claim 13 further including produce a mode shift signal once a specified number of pulses have been received from a clock and once the mode change enable signal is set.

16. The method of claim 9 further including selecting a divider ratio and dividing an oscillation by a selected value.

17. A loop filter, comprising:

resistance circuitry coupled to receive an error current;

capacitance circuitry operatively coupled to the resistance circuitry wherein the capacitance and resistance for a multi-mode loop filter having a specified bandwidth;

buffer circuitry for charging non-selected capacitors while not operationally coupled to the multi-mode loop filter; and

wherein the capacitance circuitry includes at least one capacitor selectively coupled to the buffer circuitry wherein the at least one capacitor is operatively coupled to reduce the specified bandwidth of the loop filter and to provide filtering in a steady state mode of operation of the loop filter and wherein the at least one capacitor is operatively decoupled from the loop filter in a startup mode of operation while receiving a charge from the buffer circuitry.

18. The loop filter of claim 17 wherein the resistance circuitry is operable to provide a first resistance value during the startup mode of operation and a second resistance value during a steady state mode of operation.