Efficient implementation of a filter
First Claim
1. An apparatus that includes a communication facility that executes on a processor that also employs other non-communications functionality, the apparatus comprising receive path signal processing structures, wherein at least one of the receive path signal processing structures includes at least one invocation of discrete-time filter code for filtering input vector data, the discrete-time filter code executable by the processor to incrementally load respective portions of the input vector data and coefficient vector data from addressable storage into respective registers of the processor and perform successive scalar multiply-accumulate operations thereupon to accumulate output vector data into other respective registers of the processor wherein the discrete-time filter code includes Finite Impulse Response (FIR) filter code.
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Accused Products
Abstract
A Finite Impulse Response (FIR) filter is implemented in software on a general purpose processor in a manner which reduces the number of memory accesses as compared to conventional methods. In particular, an efficient implementation for a general purpose processor having a substantial number of registers includes inner and outer loop code which together make
memory accesses and KN multiply-accumulates, where L1 is the number of output vector elements computed during each pass through the outer loop and where L2 is the number of taps per output vector element computed during each pass through the inner loop. The efficient implementation exploits L1+2L2 general purpose registers. For an embodiment in which L1=L2=8, inner and outer loop code make
memory accesses, which for filter implementations with large numbers of taps, approaches a 4× reduction in the number of memory accesses as compared to conventional methods.
35 Citations
24 Claims
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1. An apparatus that includes a communication facility that executes on a processor that also employs other non-communications functionality, the apparatus comprising receive path signal processing structures, wherein at least one of the receive path signal processing structures includes at least one invocation of discrete-time filter code for filtering input vector data, the discrete-time filter code executable by the processor to incrementally load respective portions of the input vector data and coefficient vector data from addressable storage into respective registers of the processor and perform successive scalar multiply-accumulate operations thereupon to accumulate output vector data into other respective registers of the processor wherein the discrete-time filter code includes Finite Impulse Response (FIR) filter code.
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2. A host signal processing implementation of a modem wherein at least a substantial portion of the modem implementation executes on a processor that a host system also employs for application functionality, the modem implementation comprising:
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receive path signal processing structures, wherein at least one of the receive path signal processing structures includes at least one invocation of discrete-time filter code for filtering input vector data, the discrete-time filter code executable by the processor to incrementally load respective portions of the input vector data and coefficient vector data from addressable storage into respective registers of the processor and perform successive scalar multiply-accumulate operations thereupon to accumulate output vector data into other respective registers of the processor. - View Dependent Claims (3, 4, 5, 6, 7, 8)
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9. A software modem comprising:
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receive path signal processing structures defined at least in part by instructions executable by a processor and encoded in computer readable media, wherein at least one of the receive path signal processing structures invoke discrete-time filter code for filtering input vector data, the discrete-time filter code operates on the input vector data, coefficient vector data and output vector data for which, at any given time, an operated upon portion thereof is represented entirely in registers of the processor and successive portions of the input and coefficient vector data are loaded into respective ones of the registers under control of the discrete-time filter code, and wherein the processor is a general purpose processor suitable for execution of application code concurrent with the discrete-time filter code. - View Dependent Claims (10, 11, 12, 13, 14)
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15. A method of implementing a software modem without use of a digital signal processor (DSP), the method comprising:
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receiving an output of an A/D converter; invoking discrete-time filter code for filtering input vector data, the discrete-time filter code incrementally loading respective portions of the input vector data and coefficient vector data into respective registers of a processor and performing successive operations thereupon to accumulate output vector data into other respective registers of the processor, the discrete-time filter code exhibiting an execution ratio of less than two input and coefficient data loads per operation to accumulate; and passing data to a receive process wherein the data is based at least in part on the output of the A/D converter and the output vector data. - View Dependent Claims (16, 17, 18, 19)
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20. An apparatus comprising:
- a general purpose processor having general purpose registers;
memory coupled to the general purpose processor for storing input, coefficient and output vector data; a digital-to-analog converter and an analog-to-digital converter for coupling the general purpose processor to an analog communications medium; means executable on the general purpose processor and including a discrete-time filter implementation for filtering the input vector data, the discrete-time filter implementation incrementally loading respective portions of the input and coefficient vector data into first and second sets of the general purpose registers and operating thereupon to accumulate the output vector data into a third set of the general purpose registers without use of a digital signal processor (DSP). - View Dependent Claims (21, 22, 23, 24)
- a general purpose processor having general purpose registers;
Specification