Method and system for DMA optimization in host bus adapters
First Claim
Patent Images
1. A storage area network (“
- SAN”
), comprising;
a host computing system with a host memory interfacing with a host bus adapter (HBA), where the HBA enables transfer of information to and from the host memory to a network storage system, and the HBA includes;
(a) a transmit side direct memory access (DMA) module that generates a DMA read request to transfer information stored in the host memory to the networked storage system;
(b) a receive side DMA module that generates a DMA write request that transfers information received from the networked storage system to the host memory;
(c) an arbitration module that receives the DMA read request and the DMA write request to grant access to a bus for transferring information to and from the host memory; and
(d) a DMA optimizer module that receives information from the arbitration module regarding a currently active DMA request that has been granted;
information regarding whether the currently active DMA request is a read request or a write request; and
a byte count value for the currently active DMA request;
where the DMA optimizer module adjusts a write burst size based on a first output from a DMA request monitoring logic and a second output from a logic that determines a difference between an amount of data transferred for DMA read requests and DMA write requests during a time interval;
wherein the DMA request monitoring logic determines if a DMA read or a DMA write request is pending based on a comparison of a number of clocks for DMA read requests that have not been granted by the arbitration module within a time interval to a threshold value and a comparison of a number of clocks for DMA write requests that have not been granted by the arbitration module within a time interval to a threshold value; and
the DMA request monitoring logic generates the first output based on the comparison, where the first output is used by the DMA optimizer module for adjusting the write burst size.
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Abstract
Method and system for optimizing DMA request processing is provided. The system includes a HBA that uses a dynamic DMA maximum write burst count sizing to optimize processing of write and read requests, wherein the HBA includes a DMA optimizer module that selects a certain write burst size to adjust performance when read and write DMA requests are being utilized. The DMA optimizer module can toggle between write and read request priority based on a maximum write request burst size. A shorter maximum write burst size provides more opportunity to issue read requests and a larger maximum burst size provides a better write request performance. The method includes, evaluating a read request throughput rate; evaluating a write request throughput rate; evaluating a read request utilization rate; evaluating a write request utilization rate; and adjusting a maximum write burst size.
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Citations
20 Claims
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1. A storage area network (“
- SAN”
), comprising;a host computing system with a host memory interfacing with a host bus adapter (HBA), where the HBA enables transfer of information to and from the host memory to a network storage system, and the HBA includes; (a) a transmit side direct memory access (DMA) module that generates a DMA read request to transfer information stored in the host memory to the networked storage system; (b) a receive side DMA module that generates a DMA write request that transfers information received from the networked storage system to the host memory; (c) an arbitration module that receives the DMA read request and the DMA write request to grant access to a bus for transferring information to and from the host memory; and (d) a DMA optimizer module that receives information from the arbitration module regarding a currently active DMA request that has been granted;
information regarding whether the currently active DMA request is a read request or a write request; and
a byte count value for the currently active DMA request;
where the DMA optimizer module adjusts a write burst size based on a first output from a DMA request monitoring logic and a second output from a logic that determines a difference between an amount of data transferred for DMA read requests and DMA write requests during a time interval;
wherein the DMA request monitoring logic determines if a DMA read or a DMA write request is pending based on a comparison of a number of clocks for DMA read requests that have not been granted by the arbitration module within a time interval to a threshold value and a comparison of a number of clocks for DMA write requests that have not been granted by the arbitration module within a time interval to a threshold value; and
the DMA request monitoring logic generates the first output based on the comparison, where the first output is used by the DMA optimizer module for adjusting the write burst size. - View Dependent Claims (2, 3, 4, 5, 6, 7)
- SAN”
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8. A host bus adapter (“
- HBA”
) that enables communication between a host computing system with a host memory and a networked storage system, comprising;(a) a transmit side direct memory access (DMA) module that generates a DMA read request to transfer information stored in the host memory to the networked storage system; (b) a receive side DMA module that generates a DMA write request that transfers information received from the networked storage system to the host memory; (c) an arbitration module that receives the DMA read request and the DMA write request to grant access to a bus for transferring information to and from the host memory; and (d) a DMA optimizer module that receives information from the arbitration module regarding a currently active DMA request that has been granted;
information regarding whether the currently active DMA request is a read request or a write request; and
a byte count value for the currently active DMA request;
where the DMA optimizer module adjusts a write burst size based on a first output from a DMA request monitoring logic and a second output from a logic that determines a difference between an amount of data transferred for DMA read requests and DMA write requests during a time interval;
wherein the DMA request monitoring logic determines if a DMA read or a DMA write request is pending based on a comparison of a number of clocks for DMA read requests that have not been granted by the arbitration module within a time interval to a threshold value and a comparison of a number of clocks for DMA write requests that have not been granted by the arbitration module within a time interval to a threshold value; and
the DMA request monitoring logic generates the first output based on the comparison, where the first output is used by the DMA optimizer module for adjusting the write burst size. - View Dependent Claims (9, 10, 11, 12, 13, 14)
- HBA”
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15. A method for adjusting a write burst size for write direct memory access (DMA) requests in a host bus adapter (“
- HBA”
) that enables communication between a host computing system with a host memory and a networked storage system, comprising;generating a plurality of DMA read requests for transferring information stored in the host memory to the networked storage system; generating a plurality of DMA write requests to transfer information received from the network storage system to the host memory; determining a difference between an amount of data transferred for granted DMA read requests and granted DMA write requests during a time interval; comparing a number of clocks for DMA read requests that have not been granted within a time interval to a threshold value, the comparison being used to determine if a DMA read request is pending; comparing a number of clocks for DMA write requests that have not been granted within a time interval to a threshold value, the comparison being used to determine if a DMA write request is pending; and adjusting the write burst size based on the difference between the amount of data transferred for the DMA read requests and the DMA write requests during the time interval; and
the comparison of the number of clocks for the DMA read requests that have not been granted by the arbitration module within the time interval to the threshold value and the comparison of the number of clocks for the DMA write requests that have not been granted by the arbitration module within the time interval to the threshold value. - View Dependent Claims (16, 17, 18, 19, 20)
- HBA”
Specification
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Current AssigneeMarvell Asia Pte Limited (Marvell Technology Group Limited)
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Original AssigneeQLogic Corporation (Marvell Technology Group Limited)
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InventorsGandhi, Rajendra R., Chu, Kuangfu D., Sonksen, Bradley S.
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Primary Examiner(s)Tsai; Henry
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Assistant Examiner(s)Sun; Michael
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Application NumberUS10/994,829Publication NumberTime in Patent Office1,324 DaysField of Search710/35US Class Current710/35CPC Class CodesG06F 13/28 using burst mode transfer, ...
