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Digital circuit layout techniques using binary decision diagram for identification of input equivalence

  • US 7,398,490 B2
  • Filed: 01/11/2006
  • Issued: 07/08/2008
  • Est. Priority Date: 07/17/1998
  • Status: Expired due to Term
First Claim
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1. A computer-implemented method, comprising:

  • decomposing a circuit representation into fanout-free regions, each of the fanout-free regions corresponding to at least one logic function and each of the fanout-free regions comprising an output;

    decomposing the at least one logic function of at least one of the fanout-free regions by generating a binary decision diagram for each output of the at least one of the fanout-free regions;

    identifying equivalent pins by matching pins of gates in the circuit representation with points in a ds-prime graph created using the binary decision diagram; and

    using the identified pin equivalence information to determine the input equivalence of the at least one of the fanout-free regions.

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