Electronic device including an array and process for forming the same

• US 7,399,675 B2
• Filed: 03/14/2005
• Issued: 07/15/2008
• Est. Priority Date: 10/08/2004
• Status: Expired due to Fees

• Current Assignee: North Star Innovations Inc. (Wi-LAN Inc.)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Chindalore, Gowrishankar L., Swift, Craig T.
• Primary Examiner(s): Smith, Matthew S.
• Assistant Examiner(s): Stark, Jarrett J
• Application Number:
  US11/079,674
• Publication Number:
  US 20060076609A1
• Time in Patent Office: 1,219 Days
• Field of Search: 438/201, 438/211, 438/591, 438/257, 438/266, 438/183, 438/321, 438/926, 257/202, 257/E21.679
• US Class Current: 438/266
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
• CPC Class Codes: Y10S 438/926 Dummy metallization
• CPC Class Codes: Y10S 438/962 Quantum dots and lines

Abstract

An electronic device can include an NVM array, wherein portions of word lines are formed within trenches. Insulating features are formed over heavily doped regions within the substrate. In one embodiment, charge storage stacks and a control gate electrode layer can be formed and substantially fill the trench. The insulating features help to reduce capacitive coupling between the heavily doped regions and the control gate electrode layer. In a particular embodiment, the insulating features are recessed from a top surface of a layer outside the trenches. The control gate electrode layer can form a substantially continuous electrical path along the lengths of the word lines. This particular embodiment substantially eliminates the formation of stringers or other residual etching artifacts from the control gate electrode layer within the array. A process can be performed to form the electronic device.

Claims

1. A process for forming an electronic device, the process comprising:

forming spaced-apart first insulating features over a substrate;

forming a second insulating feature over the substrate and lying between the spaced-apart first insulating features, wherein a top surface of the second insulating feature lies at a lower elevation compared to a top surface of the spaced-apart first insulating features, wherein forming the second insulating feature comprises;

depositing a first layer over the substrate including over and between the spaced-apart first insulating features;

depositing a second layer over the first layer, wherein the second layer has a different composition compared to the first layer;

removing portions of the second layer that overlie the spaced-apart first portions; and

removing portions of the first layer to lower a top surface of the first layer below the top surface of the spaced-apart first insulating features;

forming a charge storage stack overlying the second insulating feature and lying between the spaced-apart first insulating features; and

forming a control gate electrode overlying the charge storage stack and the second insulating feature and lying between the spaced-apart first insulating features.

2. The process of claim 1, wherein from a cross-sectional view,

the second insulating feature is substantially U-shaped;

a first portion the second insulating feature below the control gate electrode has a first height; and

a second portion of the second insulating feature not covered by the control gate electrode has a second height that is greater than the first height.

3. The process of claim 1, wherein the charge storage stack comprises nanocrystals.

4. The process of claim 1, further comprising removing remaining portions of the second layer before forming the charge storage stack.

5. The process of claim 1, further comprising removing portions of the first layer overlying the spaced-apart first insulating features before removing portions of the first layer to lower the top surface of the first layer.

6. The process of claim 5, wherein:

removing portions of the second layer comprises polishing the second layer;

removing portions of the first layer overlying the spaced-apart first insulating features comprises polishing the first layer; and

removing portions of the first layer to lower a top surface of the first layer comprises etching the portions first layer that lie between the spaced-apart first insulating features.

7. The process of claim 1, wherein removing portions of the first layer is performed such that the second insulating feature has a height that is in a range of approximately 20% to approximately 80% of a height of the spaced-apart first insulating features.

8. The process of claim 1, further comprising forming doped regions between the spaced-apart first insulating features before depositing the first layer.

9. The process of claim 1, wherein forming the control gate electrode comprises:

forming a control gate electrode layer over the substrate; and

polishing the control gate electrode layer to remove portions of the control gate layer overlying the spaced-apart first insulating features.

10. The process of claim 9, further comprising polishing the charge storage stack to remove portions of the charge storage stack overlying the spaced-apart first insulating features.

11. The process of claim 1, wherein forming the control gate electrode comprises:

forming a control gate electrode layer over the substrate;

forming a mask over the control gate electrode layer to define exposed portions of the control gate electrode layer; and

etching the exposed portions of the control gate electrode layer to define the control gate electrode, wherein a portion of the control gate electrode overlies at least one of the spaced-apart first insulating features after etching is completed.