ACCUFET with schottky source contact

• US 7,400,014 B2
• Filed: 04/20/2005
• Issued: 07/15/2008
• Est. Priority Date: 04/20/2004
• Status: Active Grant

• Current Assignee: Infineon Technologies Americas Corp. (Infineon Technologies AG)
• Original Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Inventors: Thapar, Naresh
• Primary Examiner(s): Menz; Douglas M
• Application Number:
  US11/110,468
• Publication Number:
  US 20060049454A1
• Time in Patent Office: 1,182 Days
• Field of Search: 257/330, 257/341
• US Class Current: 257/330
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/7828 without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An accumulation mode FET (ACCUFET) having a source contact that makes Schottky contact with the base region thereof.

Claims

1. An integrated MOSgated power semiconductor device comprising:

a graded drift region of one conductivity;

a base region of said one conductivity above said drift region;

a source region of said one conductivity above said base region;

an insulated gate adjacent said base region;

a source contact making ohmic contact with said source region and Schottky contact with said base region;

a substrate of the same conductivity as said drift region, wherein said drift region is formed over said substrate;

a drain contact electrically connected to said substrate; and

an insulated source field electrode adjacent said drift region;

wherein said insulated source field electrode and said insulated gate are disposed in a common trench.

2. A device according to claim 1, wherein said insulated source field electrode includes a source field electrode comprised of a conductive material, and an insulation body interposed between said source field electrode and said drift region.

3. A device according to claim 2, wherein said conductive material is comprised of conductive polysilicon.

4. A device according to claim 2, wherein said insulated gate includes a gate insulator and a gate electrode, said gate insulator being interposed between said base region and said gate electrode, and said insulation body being thicker than said gate insulator.

5. A device according to claim 1, further comprising a recess extending to a depth below said source region and terminates in said base region, wherein said source contact makes Schottky contact with said base region inside said recess.

6. A device according to claim 5, wherein said recess is spaced from said insulated gate.

7. A device according to claim 6, wherein said recess is adjacent an insulated source field electrode.

8. An integrated MOSgated power semiconductor device comprising:

an accumulation mode FET having an insulated gate, a graded drift region, a source contact and a base region; and

a Schottky diode, said Schottky diode being formed by a Schottky contact between said source contact and said base region; and

an insulated source field electrode adjacent said drift region;

wherein said insulated source field electrode and said insulated gate are disposed in a common trench.

9. A device according to claim 8, further comprising a recess extending to a depth below said source region and terminates in said base region, wherein said source contact makes Schottky contact with said base region inside said recess.