Formation of deep trench airgaps and related applications

• US 7,400,024 B2
• Filed: 04/20/2006
• Issued: 07/15/2008
• Est. Priority Date: 12/17/2004
• Status: Active Grant

• Current Assignee: Interuniversitair Micro-Electronica Centrum VZW (IMEC International)
• Original Assignee: Interuniversitair Micro-Electronica Centrum VZW (IMEC International)
• Inventors: Kunnen, Eddy
• Primary Examiner(s): TSAI, HUI JEY
• Application Number:
  US11/408,100
• Publication Number:
  US 20060258077A1
• Time in Patent Office: 817 Days
• Field of Search: 438400-453, 257/E27.109, 257499-564
• US Class Current: 257/511
• CPC Class Codes: H01L 21/762 Dielectric regions , e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
• CPC Class Codes: H01L 21/76289 Lateral isolation by air gap
• CPC Class Codes: H01L 21/764 Air gaps H01L21/76264 takes precedence
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2221/1094 Conducting structures comprising nanotubes or nanowires
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method for forming deep trench or via airgaps in a semiconductor substrate is disclosed comprising the steps of patterning a hole in the substrate, partly fill said hole with a sacrificial material (e.g. poly-Si), depositing spacers on the sidewalls of the unfilled part of the hole (e.g. TEOS) to narrow the opening, removing through said narrowed opening the remaining part of the sacrificial material (e.g. by isotropic etching) and finally sealing the opening of the airgap by depositing a conformal layer (TEOS) above the spacers. The method of forming an airgap is demonstrated successfully for use as deep trench isolation structures in BiCMOS devices.

Claims

1. A bipolar complementary metal oxide semiconductor device, the device comprising:

a substrate having a trench therein, the trench having walls and a bottom;

an airgap enclosed in the trench in the substrate, the airgap having a top, a bottom, and sides, wherein the top of the airgap is enclosed by a portion of spacers and a portion of a layer above the spacers, the portion of the spacers and the portion of the layer above the spacers sealing the opening of the trench;

an oxide separating layer atop the walls and the bottom of the trench;

an extra oxide liner atop the oxide separating layer, wherein the spacers are situated atop the extra oxide liner; and

a first field area and a second field area formed inside said substrate, wherein the airgap is situated between the first field area and the second field area.

2. The bipolar complementary metal oxide semiconductor device of claim 1, wherein the trench is tapered such that a width of the trench decreases deeper into the substrate.

3. The bipolar complementary metal oxide semiconductor device of claim 1, wherein the substrate comprises silicon.

4. The bipolar complementary metal oxide semiconductor device of claim 1, wherein the layer above the spacers comprises tetraethylorthosilicate.

5. The bipolar complementary metal oxide semiconductor device of claim 1, wherein at least one of the oxide separating layer and the extra oxide layer comprises tetraethylorthosilicate.

6. The bipolar complementary metal oxide semiconductor device of claim 1, wherein the spacers comprise tetraethylorthosilicate.

7. The bipolar complementary metal oxide semiconductor device of claim 1, wherein the first field area comprises a planarized first field area and wherein the second field area comprises a planarized second field area.

8. The bipolar complementary metal oxide semiconductor device of claim 1, wherein the first field area and the second field area each comprise an oxide.

9. The bipolar complementary metal oxide semiconductor device of claim 1, further comprising:

an oxide protecting layer atop a portion of the substrate adjacent to the first field area and the second field area; and

an active protecting nitride layer atop the oxide protecting layer, wherein the oxide protecting layer is configured to minimize strain effects from the active protecting nitride layer in the substrate.

10. The bipolar complementary metal oxide semiconductor device of claim 9, further comprising an oxide protecting layer atop the active protecting nitride layer.

11. A bipolar complementary metal oxide semiconductor device, the device comprising:

a substrate having a trench therein, the trench having walls and a bottom, wherein an oxide separating layer is situated atop the walls and the bottom of the trench, and an extra oxide liner is situated atop the oxide separating layer;

an airgap enclosed in the trench in the substrate, the airgap having a top, a bottom, and sides, wherein the top of the airgap is enclosed by spacers and a planarized sealing layer, wherein the spacers are situated atop the extra oxide liner;

a planarized first field area and a planarized second field area formed inside said substrate, wherein the airgap is situated between the planarized first field area and the planarized second field area.

12. The bipolar complementary metal oxide semiconductor device of claim 11, further comprising:

an oxide protecting layer atop a portion of the substrate adjacent to the planarized first field area and the planarized second field area; and

an active protecting nitride layer atop the oxide protecting layer, wherein the oxide protecting layer is configured to minimize strain effects from the active protecting nitride layer in the substrate.

13. The bipolar complementary metal oxide semiconductor device of claim 12, further comprising an oxide protecting layer atop the active protecting nitride layer.

14. The bipolar complementary metal oxide semiconductor device of claim 12, wherein the extra oxide liner has a thickness of 300 nm or less, wherein the oxide protecting layer has a thickness of up to about 25 nm, and wherein the active protecting nitride layer has a thickness of 300 nm or less.

15. The bipolar complementary metal oxide semiconductor device of claim 14, wherein the active protecting nitride layer has a thickness of from about 150 nm to about 300 nm.

16. The bipolar complementary metal oxide semiconductor device of claim 11, wherein at least one of the planarized sealing layer, the spacers, the oxide separating layer, and the extra oxide liner comprises tetraethylorthosilicate, and wherein the planarized first field area and the planarized second field area each comprise an oxide.

17. The bipolar complementary metal oxide semiconductor device of claim 16, wherein the oxide separating layer is oxidized silicon, and wherein the extra oxide layer comprises tetraethylorthosilicate.

18. The bipolar complementary metal oxide semiconductor device of claim 11, wherein a distance between the spacers is from about 50 to about 200 nm.