Analog to digital converter calibration via synchronous demodulation
First Claim
1. A digital converter apparatus comprising:
- a converter core having at least two predetermined calibration states in a calibration mode, each of the predetermined calibration states providing a respective predetermined output signal;
a control circuit for switching the converter core between at least two of the predetermined calibration states;
a sampler for providing a converter output signal over a sequence of multiple predetermined calibration states;
a synchronous demodulator for demodulating the converter output signalwherein the control circuit further switches between the calibration states at a state toggle frequency, and a bandwidth of the synchronous demodulator is centered at the state toggle frequency.
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Abstract
A technique for dynamically calibrating a successive approximation charge to digital converter by toggling at least some portion of the converter between two predetermined states, with the design goal of balancing the voltage and/or charge that is output in the two states. The two states are chosen such that they are expected to generate the same output voltage when the converter is in “normal” operation mode, e.g., within a fraction of the Least Significant Bit (LSB) resolution of the converter. If there is an imbalance, switching between the two calibration states invariably generates a square wave signal that toggles between two distinct values. A synchronous demodulator having a bandwidth centered at the toggle frequency can then be used to accurately detect an amount of error, which is then feedback to generate correction signals. If there are undesirable static offsets introduced by the synchronous demodulator or by the signal and/or charge levels output by the two differential halves of the converter, a properly timed latch can be used to further stabilize the error signal.
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Citations
18 Claims
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1. A digital converter apparatus comprising:
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a converter core having at least two predetermined calibration states in a calibration mode, each of the predetermined calibration states providing a respective predetermined output signal; a control circuit for switching the converter core between at least two of the predetermined calibration states; a sampler for providing a converter output signal over a sequence of multiple predetermined calibration states; a synchronous demodulator for demodulating the converter output signal wherein the control circuit further switches between the calibration states at a state toggle frequency, and a bandwidth of the synchronous demodulator is centered at the state toggle frequency. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. An apparatus for calibrating a digital converter comprising:
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a controller for toggling at least some portion of the converter between at least two predetermined calibration states in a calibration mode, with each of the two predetermined calibration states providing a predetermined output signal; an output circuit for providing a converter output signal over a sequence of multiple predetermined calibration states; a demodulator for synchronously demodulating the converter output signal; and an integrator for integrating the converter output signal to provide an error signal, wherein the error signal is generally a ramp type waveform in the absence of noise. - View Dependent Claims (11, 12, 13, 14, 15)
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16. An apparatus for calibrating a digital converter comprising:
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a controller for toggling at least some portion of the converter between at least two predetermined calibration states in a calibration mode, with each of the two predetermined calibration states providing a predetermined output signal; an output circuit for providing a converter output signal over a sequence of multiple predetermined calibration states; a demodulator for synchronously demodulating the converter output signal; wherein the converter is a complimentary type converter having a first conversion signal path operating as a plus signal path, and a second conversion signal path operating as a minus signal path; and wherein the two conversion signal paths are Charge Coupled Device (CCD) pipeline stages. - View Dependent Claims (17, 18)
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Specification