Programming method to reduce gate coupling interference for non-volatile memory

• US 7,400,532 B2
• Filed: 02/16/2006
• Issued: 07/15/2008
• Est. Priority Date: 02/16/2006
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Aritome, Seiichi
• Primary Examiner(s): AUDUONG, GENE NGHIA
• Application Number:
  US11/355,830
• Publication Number:
  US 20070189073A1
• Time in Patent Office: 880 Days
• Field of Search: 365/185.17, 365/185.18, 365/185.03, 365/185.23, 365/185.24
• US Class Current: 365/185.17
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/0491 Virtual ground arrays
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2211/5621 Multilevel programming verification
• CPC Class Codes: G11C 2211/5642 Multilevel memory with buffers, latches, registers at input or output
• CPC Class Codes: G11C 2216/14 Circuits or methods to write a page or sector of information simultaneously into a nonvolatile memory, typically a complete row or word line in flash memory

Abstract

A non-volatile memory device and programming process is described that compensates for coupling effects on threshold gate voltages of adjacent floating gate or non-conductive floating node memory cells by adjusting the threshold voltage level programmed in view of the data being programmed on a following programming cycle into adjacent memory cells, so that the coupling effect results in the desired target threshold voltages for the cells. In one embodiment of the present invention, memory cell coupling is compensated for by adjusting programming level of one or more memory cells of a first page a memory array to a higher or lower threshold verify target voltage given the data/programming level to be written to directly adjacent memory cells of a second page, so that coupling between the directly adjacent memory cells of the first and second pages brings the memory cells of first page to their final target programming level.

Claims

1. A method of programming non-volatile memory cells of a non-volatile memory array, comprising:

receiving a first write data and a second write data; and

adjusting the programming of the first write data into a first physical page of memory cells of a non-volatile memory array to compensate for interference by the subsequent programming of the second write data into a second physical page of memory cells of the array, wherein the memory cells of the first physical page are physically adjacent the memory cells of the second physical page in the non-volatile memory array.

2. The method of claim 1, further comprising:

programming the compensated first write data into the first physical page; and

programming the second write data into the second physical page.

3. The method of claim 1, wherein adjusting the programming of the first write data further comprises selectively adjusting a target threshold voltage to be programmed into one or more memory cells of the first physical page of the non-volatile memory array.

4. The method of claim 1, further comprising:

receiving a third write data; and

adjusting the programming of the first write data into a first physical page of memory cells of the non-volatile memory array to compensate for interference by the subsequent programming of the third write data into a third physical page of memory cells of the array.

5. The method of claim 1, wherein the non-volatile memory array is one of a NAND architecture array, a NOR architecture array, an AND architecture array, and a virtual ground architecture array.

6. The method of claim 1, wherein each memory cell of the first physical page is directly adjacent a memory cell of the second physical page of the non-volatile memory array.

7. The method of claim 1, wherein the non-volatile memory cells of the non-volatile memory array are arranged in rows and columns, and where each row of the array contains two or more pages of non-volatile memory cells.

8. The method of claim 7, wherein each page of the two or more pages of each row are arranged such that each memory cell of the page is directly adjacent a memory cell of the subsequently addressed page of the row.

9. The method of claim 7, further comprising:

addressing the two or more pages of each row of the non-volatile memory array such that each memory cell of a page being programmed is directly adjacent a memory cell of a subsequently addressed page.

10. The method of claim 9, wherein the memory cells of the pages are programmed so as to trace an “

S”

pattern in the rows and columns of the non-volatile memory array.

11. The method of claim 1, wherein the non-volatile memory cells of the non-volatile memory array are one of floating gate memory cells;

floating node memory cells;

multi-level memory cells (MLCs); and

non-conductive floating node memory cells with multiple charge storage centroids.

12. A method of programming memory cells of a non-volatile NAND architecture memory array, comprising:

receiving a first write data and a second write data;

selecting a first physical page of memory cells from a plurality of NAND architecture memory strings of the NAND architecture non-volatile memory array; and

adjusting the programming of the first write data into the first physical page of memory cells to compensate for interference by the subsequent programming of the second write data into a second adjacent physical page of memory cells of the plurality of NAND architecture memory strings of the NAND architecture non-volatile memory array.

13. The method of claim 12, further comprising:

programming the compensated first write data into the first physical page; and

programming the second write data into the second physical page.

14. The method of claim 12, wherein adjusting the programming of the first write data further comprises selectively adjusting a target threshold voltage to be programmed into one or more memory cells of the first physical page of the non-volatile NAND architecture memory array.

15. The method of claim 12, wherein the non-volatile memory cells of the non-volatile NAND architecture memory array are arranged in rows and columns and are further arranged into a plurality of NAND architecture memory cell strings.

16. The method of claim 12, wherein each memory cell of the first physical page is directly adjacent a memory cell of the second physical page of the non-volatile NAND architecture memory array.

17. The method of claim 12, wherein each row contains two or more pages of non-volatile memory cells.

18. The method of claim 17, wherein each page of the two or more pages of each row are arranged such that each memory cell of the page is directly adjacent a memory cell of the subsequently addressed page of the row.

19. The method of claim 17, further comprising:

addressing the two or more pages of each row of the non-volatile NAND architecture memory array such that each memory cell of a page being programmed is directly adjacent a memory cell of a subsequently addressed page.

20. The method of claim 12, wherein the non-volatile memory cells of the non-volatile NAND architecture memory array are one of floating gate memory cells;

floating node memory cells;

multi-level memory cells (MLCs); and

non-conductive floating node memory cells with multiple charge storage centroids.

21. A non-volatile memory device, comprising:

a non-volatile memory array having a plurality of non-volatile memory cells arranged in rows and columns;

wherein the non-volatile memory device is adapted to adjust the programming of a first data into a first physical page of memory cells of the array to compensate for interference of the first page of memory cells by the later programming of a second data into a second physical page of memory cells of the array, where the memory cells of the first physical page are physically adjacent the memory cells of the second physical page in the non-volatile memory array.

22. The non-volatile memory device of claim 21, wherein adjusting the programming of the first data further comprises selectively adjusting a target threshold voltage to be programmed into one or more memory cells of the first physical page of the non-volatile memory array.

23. The non-volatile memory device of claim 21, wherein the non-volatile memory device is adapted to adjust the programming of the first data to compensate for interference by the later programming of the third data into a third physical page of memory cells of the array.

24. The non-volatile memory device of claim 21, wherein the non-volatile memory device is one of a NAND architecture device, a NOR architecture device, an AND architecture device, and a virtual ground architecture device.

25. The non-volatile memory device of claim 21, wherein each memory cell of the first physical page is directly adjacent a memory cell of the second physical page of the non-volatile memory array.

26. The non-volatile memory device of claim 21, wherein each row of the non-volatile memory array contains two or more pages.

27. The non-volatile memory device of claim 26, wherein the two or more pages of each row of the non-volatile memory array are arranged such that each memory cell of a page is directly adjacent a memory cell of the following page of the row.

28. The non-volatile memory device of claim 27, wherein the non-volatile memory device is adapted to program the memory cells of the pages so as to trace an “

S”

pattern in the rows and columns of the non-volatile memory array.

29. The non-volatile memory device of claim 21, wherein the plurality of non-volatile memory cells are one of floating gate memory cells;

floating node memory cells;

multi-level memory cells (MLCs); and

non-conductive floating node memory cells with multiple charge storage centroids.

30. A NAND architecture non-volatile memory device, comprising:

a NAND architecture non-volatile memory array having a plurality of non-volatile memory cells arranged in rows and columns and are further arranged into a plurality of NAND architecture memory cell strings;

wherein the NAND architecture non-volatile memory device is adapted to compensate a first write data to be programmed into a first physical page of memory cells for interference due to the subsequent programming of a second write data into a second physical page of memory cells of the array, where the second physical page is adjacent to the first physical page in the array.

31. The NAND architecture non-volatile memory device of claim 30, wherein adjusting the programming of the first write data further comprises selectively adjusting a target threshold voltage to be programmed into one or more memory cells of the first physical page when an adjacent memory cell of the second physical page is to be programmed.

32. The NAND architecture non-volatile memory device of claim 30, wherein the NAND architecture non-volatile memory device is a Flash memory device.

33. The NAND architecture non-volatile memory device of claim 30, wherein each row of the non-volatile memory array contains two or more pages.

34. The NAND architecture non-volatile memory device of claim 33, wherein the two or more pages of each row of the non-volatile memory array are arranged such that each memory cell of a page is directly adjacent a memory cell of the following page of the row.

35. The NAND architecture non-volatile memory device of claim 34, wherein the NAND architecture non-volatile memory device is adapted to program the memory cells of the pages so as to trace an “

S”

pattern in the rows and columns of the non-volatile memory array.

36. The NAND architecture non-volatile memory device of claim 30, wherein the plurality of non-volatile memory cells are one of floating gate memory cells;

floating node memory cells; and

multi-level memory cells (MLCs).

37. The NAND architecture non-volatile memory device of claim 30, wherein the NAND architecture non-volatile memory array is further divided into a plurality of erase blocks and where the NAND architecture non-volatile memory device is adapted to program the first and second page in a selected memory block of the non-volatile memory array.

38. A NAND architecture non-volatile memory device, comprising:

a NAND architecture non-volatile memory array having a plurality of non-volatile memory cells arranged in rows and columns, wherein the plurality of non-volatile memory cells are coupled into a plurality of NAND architecture memory cell strings; and

a control circuit, wherein the control circuit is adapted to program a first write data into a first physical page of memory cells of the non-volatile memory array and a second write data into an adjacent second physical page of memory cells of the non-volatile memory array by,

compensating the target threshold voltage levels of the first write data to be programmed into the first physical page of memory cells for interference due to the target threshold data values of a second data to be programmed into the adjacent second physical page;

selecting the first physical page in one or more NAND architecture memory cell strings for programming of non-volatile memory array, where the selected memory cell in each of the one or more memory cell strings is coupled to a word line,

applying a program voltage to the word line coupled to the selected memory cells of the first physical page,

applying a pass voltage to one or more unselected word lines coupled to one or more unselected memory cells of the one or more memory cell strings, and

verifying the adjusted threshold voltage values stored in the first physical page against the first write data.

39. The NAND architecture non-volatile memory device of claim 38, wherein the control circuit is adapted to program a first write data into a first physical page of memory cells of the non-volatile memory array and a second write data into an adjacent second physical page of memory cells of the non-volatile memory array by,

selecting the second physical page in one or more NAND architecture memory cell strings for programming of non-volatile memory array, where the selected memory cell in each of the one or more memory cell strings is coupled to a word line,

applying a program voltage to the word line coupled to the selected memory cells of the second physical page,

applying a pass voltage to one or more unselected word lines coupled to one or more unselected memory cells of the one or more memory cell strings, and

verifying the threshold voltage values stored in the second physical page against the second write data.

40. The NAND architecture non-volatile memory device of claim 38, wherein each row of the non-volatile memory array contains two or more pages.

41. The NAND architecture non-volatile memory device of claim 40, wherein the two or more pages of each row of the non-volatile memory array are arranged such that each memory cell of a page is directly adjacent a memory cell of the following page of the row.

42. The NAND architecture non-volatile memory device of claim 41, wherein the control circuit is adapted to program the memory cells of the pages so as to trace an “

S”

pattern in the rows and columns of the non-volatile memory array.

43. The NAND architecture non-volatile memory device of claim 38, wherein the plurality of non-volatile memory cells are one of floating gate memory cells;

floating node memory cells; and

multi-level memory cells (MLCs).

44. A system comprising:

a host coupled to a non-volatile memory device, wherein the non-volatile memory device comprises,

a NAND architecture non-volatile memory array having a plurality of non-volatile memory cells arranged in rows and columns and further arranged into a plurality of NAND architecture memory cell strings;

wherein the system is adapted to compensate a first write data to be programmed into a first physical page of memory cells of the array for interference due to the subsequent programming of a second write data into a second physical page of memory cells of the array, where the second physical page is adjacent to the first physical page in the array.

45. The system of claim 44, wherein the host is one of a processor and a memory controller.

46. The system of claim 44, wherein each row of the NAND architecture non-volatile memory array contains two or more pages.

47. The system of claim 46, wherein the two or more pages of each row of the NAND architecture non-volatile memory array are arranged such that each memory cell of a page is directly adjacent a memory cell of the following page of the row.

48. The system of claim 47, wherein the non-volatile memory device is adapted to program the memory cells of the pages so as to trace an “

S”

pattern in the rows and columns of the NAND architecture non-volatile memory array.

49. A memory module, comprising:

a plurality of contacts; and

two or more memory devices, each having access lines selectively coupled to the plurality of contacts;

wherein at least one of the memory devices comprises;

a NAND architecture non-volatile memory array having a plurality of non-volatile memory cells arranged in rows and columns and further arranged into a plurality of NAND architecture memory cell strings;

wherein the non-volatile memory device is adapted to compensate a first write data to be programmed into a first physical page of memory cells for interference due to the subsequent programming of a second write data into a second physical page of memory cells of the array, where the second physical page is adjacent to the first physical page in the array.

50. A memory module, comprising:

a housing having a plurality of contacts; and

one or more non-volatile NAND architecture memory devices enclosed in the housing and selectively coupled to the plurality of contacts;

wherein the memory module is adapted to program memory cells in a selected block of at least one of the non-volatile NAND architecture memory devices by,

receiving a first write data and a second write data;

selecting a first physical page of memory cells from a plurality of NAND architecture memory strings of the NAND architecture non-volatile memory array; and

adjusting the programming of the first write data into the first physical page of memory cells to compensate for interference by the subsequent programming of the second write data into a second adjacent physical page of memory cells of the plurality of NAND architecture memory strings of the NAND architecture non-volatile memory array.