Integrated voice-over-internet protocol processor

• US 7,400,617 B1
• Filed: 09/13/2000
• Issued: 07/15/2008
• Est. Priority Date: 09/13/1999
• Status: Expired due to Fees

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies North America Corporation (Infineon Technologies AG)
• Inventors: Preiss, Frank
• Primary Examiner(s): Pham; Chi
• Assistant Examiner(s): MEW, KEVIN D
• Application Number:
  US09/660,882
• Time in Patent Office: 2,862 Days
• Field of Search: 370/401, 370/352, 370/351, 370/463, 370/465, 370/466, 370/356, 370/423
• US Class Current: 370/352
• CPC Class Codes: H04L 12/66 Arrangements for connecting between networks having differing types of switching systems, e.g. gateways

Abstract

A single-chip network processor (12) for a Voice-over-Internet Protocol phone integrates a universal serial bus port (21), a pair of IEEE 802.3 MACs (40), and repeater, and a pair of pulse code modulation (PCM) ports (24) such that the network processor can be easily combined with other peripherals to transmit both voice and computer data over an Internet protocol network.

Claims

1. A processor for use in a Voice-over-Internet Protocol telephone, including:

an internal bus for routing of signals in the processor;

a processing core to control the processor to transmit computer data and voice data over a computer network, the processor core including one or more pipelines to execute instructions, the processing core directly coupled to the internal bus;

an on-chip memory directly coupled to the internal bus and separate from the processing core, the on-chip memory including a program memory to include instruction for execution by the processing core and a data memory to store cache for the processing core;

a pulse code modulation (PCM) interface directly coupled to the internal bus and separate from the processing core and on-chip memory, the PCM interface including a PCM communication port for connection to an external voice codec;

an Ethernet interface directly coupled to the internal bus and separate from the processing core, on-chip memory and PCM interface, the Ethernet interface including a repeater, one or more IEEE 802.3 media access controllers (MACs) and an Ethernet port for connection to an external network;

an external bus unit directly coupled to the internal bus and separate from the processing core, on-chip memory, PCM interface and Ethernet interface, the external bus unit providing a bridge for connection through a device bus, other than the external network, to an external memory,

wherein the instructions are configured such that when executed by the CPU,

PCM coded speech data received by the PCM interface is transported to the external memory, read from the external memory by the processing core and compressed by the processing core and written back to the external memory, and voice data packets with such speech data are read from the external memory and forwarded to the 802.3 MAC and fed into the external network by the repeater, and

voice data packets received by the Ethernet interface are transported to the external memory, read from the external memory by the processing core and decompressed by the processing core and written back to the external memory, and PCM coded speech data from the received voice data packets is transported by the PCM interface to the external voice codec,

and wherein the internal bus, processing core, on-chip memory, PCM interface, Ethernet interface, and the external bus unit are integrated into a single chip.

2. The processor of claim 1, further comprising one or more universal serial bus (USB) ports.

3. The processor of claim 1, wherein one or more communication ports allow the processor core to be coupled to one or more external components without external interfacing circuitry.

4. The processor of claim 1, wherein each Ethernet port is operable to handle up to 30 time slots, and wherein each time slot is capable of handling a 64K bit/sec voice channel.

5. The processor of claim 1, wherein at least one pipeline supports one of arithmetic, load and store, and loop control operations for the processor core.

6. The processor of claim 1, wherein at least one pipeline is configured to execute at least one of integer instructions, bit operations, MAC instructions and conditional data jumps.

7. The processor of claim 1, wherein at least one pipeline is configured to execute load and store instructions, context operations, system instructions, address arithmetic and conditional and unconditional address instructions for the processor core.

8. The processor of claim 1, wherein at least one pipeline includes a loop hardware cache buffer operable to store location, target and minimal set of information required to execute repetitive loop within the at least one pipeline so as to achieve loop optimization.

9. The processor of claim 1, wherein the processor core includes separate address and data buses for the program memory and the data memory.

10. The processor of claim 1, wherein the internal bus is a flexible peripheral interconnect (FPI) bus.

11. The processor of claim 10, wherein the FPI bus is a demultiplexed, pipelined bus.