Switch apparatus, switchable power amplification apparatus, and mobile communication terminal apparatus using the same

• US 7,400,863 B2
• Filed: 02/14/2005
• Issued: 07/15/2008
• Est. Priority Date: 02/19/2004
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Sony Corporation (Sony Group Corp.), Sony Ericsson Mobile Communications Japan Incorporated (Sony Group Corp.)
• Inventors: Kobayashi, Tomoo, Shimada, Masayuki, Koimori, Toshiyuki, Kusunoki, Shigeo
• Primary Examiner(s): Trinh; Sonny
• Application Number:
  US11/056,266
• Publication Number:
  US 20050186919A1
• Time in Patent Office: 1,247 Days
• Field of Search: 455/78, 455/80, 455/82, 455/552.1, 455/73, 455/83, 455/168.1, 455/560, 455/550.1, 455/188.1
• US Class Current: 455/78
• CPC Class Codes: H03F 1/0277 Selecting one or more amplifiers from a plurality of amplifiers
• CPC Class Codes: H03F 1/56 Modifications of input or output impedances, not otherwise provided for
• CPC Class Codes: H03F 2200/222 A circuit being added at the input of an amplifier to adapt the input impedance of the amplifier
• CPC Class Codes: H03F 2200/318 A matching circuit being used as coupling element between two amplifying stages
• CPC Class Codes: H03F 2200/387 A circuit being added at the output of an amplifier to adapt the output impedance of the amplifier
• CPC Class Codes: H03F 2200/451 the amplifier being a radio frequency amplifier
• CPC Class Codes: H03F 2203/21136 An input signal of a power amplifier being on/off switched
• CPC Class Codes: H03F 2203/21175 An output signal of a power amplifier being on/off switched
• CPC Class Codes: H03F 3/19 with semiconductor devices only
• CPC Class Codes: H03F 3/211 using a combination of several amplifiers H03F3/60 takes precedence
• CPC Class Codes: H03F 3/245 with semiconductor devices only
• CPC Class Codes: H03F 3/72 Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
• CPC Class Codes: H03G 1/0088 using discontinuously variable devices, e.g. switch-operated
• CPC Class Codes: H03K 17/162 without feedback from the output circuit to the control circuit
• CPC Class Codes: H03K 17/693 Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors logic circuits H03K19/00; code converters H03M5/00, H03M7/00

Abstract

A switch apparatus of the invention comprises a first input terminal, a second input terminal to which a second input signal having a level lower than a level of the first input signal is supplied, a first switch block for outputting the first input signal supplied from the first input terminal through a plurality of switching elements, a second switch block for outputting the second input signal supplied from the second input terminal through a plurality of switching elements; and a control terminal to which a control signal is supplied wherein the control signal controls the first switch block when outputting the first input signal, and controls the second switch block when outputting the second input signal, wherein the first switch block is configured to have a smaller number of switching elements than that of the second switch block.

Claims

1. A switch apparatus comprising:

a first input terminal to which a first input signal is supplied;

a second input terminal to which a second input signal having a level lower than a level of the first input signal is supplied;

a first switch block configured to output the first input signal supplied from the first input terminal through a plurality of switching elements;

a second switch block configured to output the second input signal supplied from the second input terminal through a plurality of switching elements; and

a control terminal to which a control signal is supplied wherein the control signal controls the first switch block when outputting the first input signal, and controls the second switch block when outputting the second input signal, wherein

the first switch block is configured to have a smaller number of switching elements than that of the second switch block.

2. The switch apparatus as cited in claim 1, further comprising:

a first isolation enhancing circuit connected to the first switch block configured to enhance an isolation of the first switch block by activating when the second switch block is controlled by the control signal; and

a second isolation enhancing circuit connected to the second switch block configured to enhance an isolation of the second switch block by activating when the first switch block is controlled by the control signal.

3. The switch apparatus as cited in claim 1, further comprising:

a first termination circuit connected to the first switch block configured to terminate the first switch block by activating when the second switch block is controlled by the control signal; and

a second termination circuit connected to the second switch block configured to terminate the second switch block by activating when the first switch block is controlled by the control signal.

4. A switch apparatus comprising:

a first switch block in which a drain of a first FET, where a source of the first FET is connected to a first input terminal, is connected to a source of a second FET, a drain of the second FET is connected to a source of a third FET, a drain of a similarly connected Mth FET (M is a natural number) is connected to an output, and all gates of FETs of the first switch block are set to be a first control terminal by mutually connecting; and

a second switch block in which a drain of a fourth FET, where a source of the fourth FET is connected to a second input terminal, is connected to a source of a fifth FET, a drain of the fifth FET is connected to a source of a sixth FET, a drain of a similarly connected Nth FET (N is a natural number) is connected to the output, and all gates of the FETs of the second switch block are set to be a second control terminal by mutually connecting, wherein

a relation between the number M of the FETs included in the first switch block and the number N of the FETs included in the second switch block is set to be M<

N.

5. The switch apparatus as cited in claim 4, further comprising:

a seventh FET in which a gate is connected to the second control terminal, a drain is connected to the first input terminal, and a source is connected to ground;

a first matching circuit connected between the source of the seventh FET and ground;

an eighth FET in which a gate is connected to the first control terminal, a drain is connected to the second input terminal, and a source is connected to ground; and

a second matching circuit connected between the source of the eighth FET and ground.

6. The switch apparatus as cited in claim 5, wherein

the first matching circuit is a termination matching circuit of the first switch block, and

the second matching circuit is a termination matching circuit of the second switch block.

7. A switch apparatus comprising:

a first switch block in which all sources of M FETs (where M is a natural number) are connected to be a first input terminal, all drains of the M FETs are connected to be an output terminal, and all gates of the M FETs are connected to be a first control terminal; and

a second switch block in which a drain of a first FET, where a source of the first FET is connected to a second input terminal is connected to a source of a second FET, a drain of the second FET is connected to a source of a third FET, a drain of a similarly connected Nth FET (N is a natural number) is connected to the output terminal, and all gates of the FETs are set to be a second control terminal by mutually connecting, wherein

a relation between the number M of the FETs included in the first switch block and the number N of the FETs included in the second switch block is set to be M<

N.

8. A switchable power amplifier apparatus comprising:

a first amplifier element configured to amplify an input signal;

a second amplifier element configured to further amplify the input signal amplified in the first amplifier element and supply the input signal to a first output terminal;

a first switch element configured to perform an on/off operation based on a control signal for setting the second amplifier element in an operating condition by supplying the input signal from the first amplifier element when performing an on operation, and configured to set the second amplifier element in a non-operating condition by not supplying the input signal from the first amplifier element when performing an off operation;

a second switch element configured to perform an on/off operation based on a control signal, but opposite to the operation of the first switch element, to supply the input signal from the first amplifier element to a second output terminal when performing an on operation, and to stop the supply of the input signal to the second output terminal when performing an off operation;

a first switch block configured to perform an on operation based on the control signal for setting the first switch element in an on operation and to output through a plurality of switch elements a first input signal supplied through the first output terminal; and

a second switch block configured to perform an on operation based on the control signal for setting the second switch element in an on operation and to output through a second plurality of switch elements a second input signal, a level of which is lower than that of the first input signal, supplied through the second output terminal, wherein

a number of switch elements included in the second switch block is larger than a number of switch elements included in the first switch block.

9. The switchable power amplifier apparatus as cited in claim 8, wherein

the first amplifier element includes a FET in which a source is connected to ground, and an output having a level amplified in response to the input signal supplied to a gate of the FET is derived from a drain of the FET, and further comprising:

a power adjustment circuit configured to superpose a power adjustment signal, having a level larger than that of when the control signal sets the second amplifier element into an operating condition, onto the input signal supplied to the gate of the first amplifier element when the control signal for setting the second amplifier element into a non-operating condition is supplied to the first switch element.

10. The switchable power amplifier apparatus as cited in claim 8 or claim 9, further comprising:

a phase adjustment circuit configured to adjust the input signal so that a phase of the input signal amplified by the first amplifier element and the second amplifier element and supplied to the first output terminal, and the input signal amplified only by the first amplifier element and supplied to the second output terminal become the same phase.

11. The switchable power amplifier apparatus as cited in claim 8 or claim 9, further comprising:

a first isolation enhancing circuit connected to the first switch block configured to enhance an isolation of the first switch block by activating when the second switch block is controlled by the control signal; and

a second isolation enhancing circuit connected to the second switch block configured to enhance an isolation of the second switch block by activating when the first switch block is controlled by the control signal.

12. The switchable power amplifier apparatus as cited in claim 8 or claim 9, further comprising:

a first termination circuit connected to the first switch block configured to terminate the first switch block by activating when the second switch block is controlled by the control signal; and

a second termination circuit connected to the second switch block configured to terminate the second switch block by activating when the first switch block is controlled by the control signal.

13. The switchable power amplifier apparatus as cited in claim 8 or claim 9, including the first amplifier element, the second amplifier element, the first switch element, the second switch element, the first switch block, and the second switch block configured to be formed on one chip based on a high mobility electron transistor formed by:

a high mobility electron channel formed near a hetero-junction between two semiconductor layers of a plurality of semiconductor layers stacked on a semiconductor substrate forming a channel of the high mobility electron transistor;

a contact semiconductor layer, which is made of impurity doped semiconductor material, formed on at least one side surface of the plurality of the semiconductor layers; and

a source electrode or a drain electrode formed through an ohmic contact layer on the contact semiconductor layer.

14. A mobile communication terminal apparatus which converts a transmission output of a transmission signal to a plurality of transmission outputs by a power amplifier circuit, and transmits one of the transmission outputs by selecting a selection switch, wherein

the power amplifier circuit comprises:

a first amplifier element configured to amplify the transmission signal,

a second amplifier element configured to further amplify the transmission signal amplified in the first amplifier element and supply the transmission signal to a first output terminal,

a first switch element performing an on/off operation based on a control signal configured to set the second amplifier element in an operating condition by supplying the transmission signal from the first amplifier element when performing on operation, and setting the second amplifier element in a non-operating condition by not supplying the transmission signal from the first amplifier element when performing an off operation, and

second switch element configured to perform an on/off operation based on a control signal, but opposite to the operation of the first switch element, to supply the transmission signal from the first amplifier element to a second output terminal when performing an on operation, and to stop the supply of the transmission signal to the second output terminal when performing an off operation; and

said selection switch comprises;

a first switch block configured to perform an on operation based on the control signal for setting the first switch element in performing an on operation and to output through a plurality of switch elements a first transmission signal supplied through the first output terminal, and

a second switch block configured to perform an on operation based on the control signal for setting the second switch element in performing an on operation and to output through a second plurality of switch elements a second transmission signal, a level of which is lower than that of the first transmission signal, supplied through the first output terminal, wherein a number of switch elements included in the second switch block is larger than a number of switch elements included in the first switch block.

15. The mobile communication terminal apparatus as cited in claim 14, wherein

the first amplifier element includes a FET in which a source is connected to ground, and an output having a level amplified in response to the input signal supplied to a gate is derived from a drain, and further comprising:

a power adjustment circuit configured to superpose a power adjustment signal, having a level larger than that of when the control signal sets the second amplifier element into operating condition, onto the input signal supplied to the gate of the first amplifier element when the control signal for setting the second amplifier element into non-operating condition is supplied to the first switch element.

16. The mobile communication terminal apparatus as cited in claim 14 or claim 15, further comprising:

a phase adjustment circuit configured to adjust the input signal so that a phase of the input signal amplified by the first amplifier element and the second amplifier element and supplied to the first output terminal, and the input signal amplified only by the first amplifier element and supplied to the second output terminal become the same phase.

17. The mobile communication terminal apparatus as cited in claim 14 or claim 15, further comprising:

a first isolation enhancing circuit connected to the first switch block configured to enhance an isolation of the first switch block by activating when the second switch block is controlled by the control signal; and

a second isolation enhancing circuit connected to the second switch block configured to enhance an isolation of the second switch block by activating when the first switch block is controlled by the control signal.

18. The mobile communication terminal apparatus as cited in claim 14 or claim 15, further comprising:

a first termination circuit connected to the first switch block configured to terminate the first switch block by activating when the second switch block is controlled by the control signal; and

a second termination circuit connected to the second switch block configured to terminate the second switch block by activating when the first switch block is controlled by the control signal.

19. The mobile communication terminal apparatus as cited in claim 14 or claim 15 including the first amplifier element, the second amplifier element, the first switch element, the second switch element, the first switch block, and the second switch block configured to be formed on one chip having the power amplifier circuit and the selection circuit formed based on a high mobility electron transistor formed by:

a high mobility electron channel formed near a hetero-junction between two semiconductor layers of a plurality of semiconductor layers stacked on a semiconductor substrate for forming a channel of a transistor;

a contact semiconductor layer, which is made of impurity doped semiconductor material, formed on at least one side surface of the plurality of the semiconductor layers; and

a source electrode or a drain electrode formed through an ohmic contact layer on the contact semiconductor layer.