Semiconductor device and process for producing the same

• US 7,402,473 B2
• Filed: 04/19/2005
• Issued: 07/22/2008
• Est. Priority Date: 02/18/1997
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Hitachi ULSI Systems Company Limited (Hitachi, Ltd.), Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Ikeda, Shuji, Suzuki, Norio, Yoshida, Yasuko, Miura, Hideo, Yamamoto, Hirohiko, Takamatsu, Akira, Kobayashi, Masamichi, Ishitsuka, Norio, Shimizu, Hirofumi, Matsuda, Yasushi, Nozoe, Toshio, Horibe, Shinichi, Fukuda, Kazushi
• Primary Examiner(s): Quach; Tuan N.
• Application Number:
  US11/108,827
• Publication Number:
  US 20050196935A1
• Time in Patent Office: 1,190 Days
• Field of Search: 438424-426, 438/435, 438/437, 438/585, 438/589, 438/197, 438/218, 438/221, 257/E21.546
• US Class Current: 438/197
• CPC Class Codes: H01L 21/76232 of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls H01L21/76229 takes precedence
• CPC Class Codes: H01L 21/76235 trench shape altered by a local oxidation of silicon process step, e.g. trench corner rounding by LOCOS
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

A process of producing a semiconductor device having a highly reliable groove isolation structure with a desired radius of curvature formed at the groove upper edge and without formation of any step. The device is produced by reducing the stress generation around the groove upper edge of an element isolation groove on a semiconductor substrate, thereby optimizing the shape of an element isolation groove and making the device finer and improving the device electric characteristics.

Claims

1. A process for producing a semiconductor device, comprising:

forming a first oxide film on a semiconductor substrate by a first oxidizing process of the semiconductor substrate,

forming a silicon nitride film on the first oxide film,

forming a photoresist film on the silicon nitride film,

removing a portion of the photoresist film,

removing the silicon nitride film and the first oxide film at the removed portion of the photoresist film,

trenching a groove at an angle of 95°

to 110°

of the inside wall of the groove to the surface of the semiconductor substrate in an element isolation region in a portion of the semiconductor substrate from which the first oxide film is removed,

removing another portion of the photoresist film on the silicon nitride film,

forming a recessed space under the silicon nitride film by etching the first oxide film from the region where the groove is formed,

forming a second oxide film in the recessed space by thermally oxidizing the semiconductor substrate to a degree not greater than the amount of oxidation that develops upward warping deformation of the silicon nitride film, and

embedding a third oxide film in the groove, removing the silicon nitride film and the first oxide film on the semiconductor substrate, and forming a gate dielectric film and a gate electrode on the semiconductor substrate.

2. A process according to claim 1, wherein the recessed space is formed to an extent of 5 nm to 40 nm from the element isolation region.

3. A process according to claim 2, wherein the second oxide film is formed so that the radius of curvature of the semiconductor substrate around an upper edge of the groove is 3 nm or more.

4. A process according to claim 1, wherein the second oxide film is formed so that the radius of curvature of the semiconductor substrate around an upper edge of the groove is 3 nm or more.

5. A process for producing a semiconductor device, comprising:

forming a pad oxide film on a circuit forming side of a semiconductor substrate,

forming an anti-oxidation film on the pad oxide film,

forming a photoresist film on the anti-oxidation film,

removing portions of the anti-oxidation film and the pad oxide film,

trenching a groove at an angle of 95°

to 110°

of the inside wall of the groove to the surface of the semiconductor substrate in a portion of the semiconductor substrate from which the pad oxide film has been removed while masking an element region,

removing a portion of the photoresist film,

removing another portion of the photoresist film on the anti-oxidation film,

forming a space to an extent of 5 to 40 nm on the semiconductor surface around the groove by etching the pad oxide film from the side wall of the groove,

forming a second silicon oxide film by oxidation in the recessed space, wherein the oxidation is carried for a sufficient time until a lower surface of the recessed space and a surface in the groove are fully covered by the second oxide film, and wherein the oxidation is stopped at or before a time when the recessed space is completely filled by said second silicon oxide film,

embedding an element isolation film in the groove having the second oxide film,

removing the anti-oxidation film and the pad oxide film on the semiconductor substrate,

forming a gate dielectric film on the surface of the semiconductor substrate in the element isolation region, and

forming a gate electrode on the gate dielectric film.

6. A process according to claim 5, wherein the second silicon oxide film is formed so that the radius of curvature of the semiconductor substrate around an upper edge of the groove is 3 nm or more.