Trench FET with reduced mesa width and source contact inside active trench

• US 7,402,863 B2
• Filed: 06/21/2005
• Issued: 07/22/2008
• Est. Priority Date: 06/21/2004
• Status: Active Grant

• Current Assignee: Infineon Technologies Americas Corp. (Infineon Technologies AG)
• Original Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Inventors: Jones, David P.
• Primary Examiner(s): WOJCIECHOWICZ, EDWARD JOSEPH
• Application Number:
  US11/157,371
• Publication Number:
  US 20050280079A1
• Time in Patent Office: 1,127 Days
• Field of Search: 257/330, 257/331, 257/332, 257/401, 257/413, 257/754, 257/773
• US Class Current: 257/331
• CPC Class Codes: H01L 29/0865 Disposition
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A trench FET has source contacts which contact the entire top surface of source regions, and contact a portion of side walls of the source regions. The side walls of the source regions form a portion of the side walls of the trenches in the trench FET.

Claims

1. A trench-type MOSFET comprising

a plurality of spaced gate trenches, each gate trench including an insulated gate electrode, said plurality of gate trenches defining a plurality of mesas, each of said mesas being between a pair of opposing gate trenches;

a plurality of source regions of a first conductivity formed in each mesa, each source region having a first portion exposed at a sidewall of a gate trench, and a second portion exposed at a top surface of a mesa, said source regions being formed over a channel region of a second conductivity, said channel region being adjacent said gate trenches; and

a high conductivity contact region of said second conductivity in each mesa between a pair of source regions;

a silicide contact layer over each mesa and in contact with first and second portions of said pair of source regions and said high conductivity contact region therebetween;

a source contact comprised of metal formed over said silicide contact layer over each mesa, and extending inside each gate trench, wherein said source contact is insulated from said gate electrodes inside said gate trenches.

2. A trench-type MOSFET of claim 1, wherein said gate electrode is comprised of polysilicon.

3. A trench-type MOSFET of claim 1, wherein said gate insulation is comprised of silicon dioxide.