Lateral undercut of metal gate in SOI device

• US 7,402,875 B2
• Filed: 08/17/2005
• Issued: 07/22/2008
• Est. Priority Date: 08/17/2005
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Chau, Robert S., Doczy, Mark L., Dewey, Gilbert, Kavalieros, Jack, Doyle, Brian S., Brask, Justin K., Datta, Suman
• Primary Examiner(s): WOJCIECHOWICZ, EDWARD JOSEPH
• Application Number:
  US11/207,051
• Publication Number:
  US 20070040223A1
• Time in Patent Office: 1,070 Days
• Field of Search: 257/368, 257/321, 257/340, 257/347, 257/388, 257/401
• US Class Current: 257/401
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/495 the conductor material next to the insulator being a simple metal, e.g. W, Mo H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78654 Monocrystalline silicon transistors

Abstract

Embodiments of the invention provide a device with a metal gate, a high-k gate dielectric layer, source/drain extensions a distance beneath the metal gate, and lateral undercuts in the sides of the metal gate.

Claims

1. A semiconductor device, comprising:

a first semiconductor substrate;

an insulator layer on the semiconductor substrate;

a second semiconductor layer on the insulator layer;

a dielectric layer on the second semiconductor layer; and

a metal layer on the dielectric layer, wherein the metal layer includes curved lateral undercuts that are deepest around a center of the metal layer'"'"'s thickness and that taper off towards a top and a bottom surface of the metal layer so the metal layer has an effective length less than a length of the dielectric layer.

2. The device of claim 1, further comprising a conductive layer on the metal layer, wherein the effective length of the metal layer is less than a length of the conductive layer.

3. The device of claim 1, wherein the metal layer is a metal gate electrode and the device is a transistor.

4. The device of claim 3, further comprising:

a source region on a first side of the second semiconductor layer, the source region extending a first distance under the dielectric layer;

a drain region on a second side of the second semiconductor layer, the drain region extending a second distance under the dielectric layer, the second distance being about equal to the first distance; and

wherein the lateral undercuts in the metal layer extend at least about one quarter the first distance on the first side and at least about one quarter the second distance on the second side.

5. The device of claim 4, wherein the lateral undercuts in the metal layer extend between about one quarter the first distance and about three-quarters the first distance on the first side and between about one quarter the second distance and about three-quarters the second distance on the second side.

6. The device of claim 4, further comprising spacers on first and second sides of the metal layer, the spacers filling the lateral undercuts in the metal layer.

7. The device of claim 1, wherein the metal layer has a thickness between about 50 angstroms and about 200 angstroms.

8. The device of claim 7, wherein the metal layer has a maximum length of about 30-35 nanometers.

9. The device of claim 1, wherein the metal layer has a thickness of at least about 75 angstroms.

10. The device of claim 1, wherein dielectric layer has a thickness less than about 30 angstroms.

11. A semiconductor device, comprising:

a first semiconductor layer;

an insulating layer on the semiconductor substrate;

a second semiconductor layer on the insulator layer;

a dielectric layer on the second semiconductor layer;

a metal gate on the dielectric layer, wherein the metal gate has curved lateral undercuts extending into a center of the metal gate'"'"'s thickness and tapering off towards a top and a bottom surface of the metal gate, wherein each lateral undercut has a depth laterally measured from an outermost edge of the metal gate to a greatest depth of the lateral undercut;

source and drain regions of the second semiconductor layer on either side of the metal gate, wherein the source and drain regions have extensions that go a lateral depth under the metal gate measured from the outermost edge of the metal gate to a furthest depth of the extension; and

wherein the depth of the lateral undercuts is less than the depth of the source and drain region extensions.

12. The device of claim 11, wherein the dielectric layer comprises a high-k dielectric material.

13. The device of claim 12, wherein the metal gate comprises a mid-gap metal gate material.

14. The device of claim 11, wherein the metal gate has a thickness of at least about 50 angstroms.

15. The device of claim 14, wherein the metal gate has a maximum length of about 30-35 nanometers and the depth of the lateral undercuts is between about 7.5 and about 3.5 nanometers.

16. The device of claim 15, wherein dielectric layer comprises a high-k dielectric material and has a thickness less than about 30 angstroms.