Vertical system integration

• US 7,402,897 B2
• Filed: 08/08/2003
• Issued: 07/22/2008
• Est. Priority Date: 08/08/2002
• Status: Expired due to Fees

• Current Assignee: ELM TECHNOLOGY CORPORATION
• Original Assignee: ELM TECHNOLOGY CORPORATION
• Inventors: Leedy, Glenn J.
• Primary Examiner(s): MENZ, LAURA MARY
• Application Number:
  US10/485,046
• Publication Number:
  US 20050023656A1
• Time in Patent Office: 1,810 Days
• Field of Search: 257/678, 257/686, 257/109, 438/106
• US Class Current: 257/678
• CPC Class Codes: B81B 7/02 containing distinct electrical or optical devices of particular relevance for their function, e.g. microelectro-mechanical systems [MEMS] B81B7/04 takes precedence
• CPC Class Codes: B81C 1/00238 Joining a substrate with an electronic processing unit and a substrate with a micromechanical structure
• CPC Class Codes: B81C 1/00246 Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate
• CPC Class Codes: B81C 2203/0771 Stacking the electronic processing unit and the micromechanical structure
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: H01L 21/8252 the substrate being a semiconductor, using III-V technology H01L21/8258 takes precedence
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2223/54453 for use prior to dicing
• CPC Class Codes: H01L 2223/6677 for antenna, e.g. antenna included within housing of semiconductor device
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 2225/06596 Structural arrangements for testing
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/52 Arrangements for conducting electric current within the device in operation from one component to another , i.e. interconnections, e.g. wires, lead frames optical interconnections G02B6/00
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 27/0688 : Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/118 : Masterslice integrated circuits
• CPC Class Codes: H01L 27/11803 : using field effect technology
• CPC Class Codes: H01L 27/1203 : the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1463 : Pixel isolation structures
• CPC Class Codes: H01L 27/14643 : Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 27/14683 : Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof not peculiar thereto H01L21/00
• CPC Class Codes: H01L 29/40114 : the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/40117 : the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/42324 : Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/42328 : with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/66825 : with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66833 : with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7827 : Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7831 : with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645
• CPC Class Codes: H01L 29/78648 : arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/7881 : Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H04W 4/80 : Services using short range communication, e.g. near-field communication [NFC], radio-frequency identification [RFID] or low energy communication
• CPC Class Codes: H10B 12/00 : Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/20 : DRAM devices comprising floating-body transistors, e.g. floating-body cells
• CPC Class Codes: H10B 12/30 : DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
• CPC Class Codes: H10B 69/00 : Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

The Vertical System Integration (VSI) invention herein is a method for integration of disparate electronic, optical and MEMS technologies into a single integrated circuit die or component and wherein the individual device layers used in the VSI fabrication processes are preferably previously fabricated components intended for generic multiple application use and not necessarily limited in its use to a specific application. The VSI method of integration lowers the cost difference between lower volume custom electronic products and high volume generic use electronic products by eliminating or reducing circuit design, layout, tooling and fabrication costs.

Claims

1. A method of making a stacked integrated circuit comprising:

providing a design library comprising a plurality of physical IC designs of fabricated circuit layers, wherein a circuit layer is from the group of an integrated circuit and a stacked integrated circuit; and

using at least one circuit layer from the design library to fabricate the stacked integrated circuit, wherein said circuit layer is designed with interconnections that are completed during fabrication of the stacked integrated circuit and said interconnections pass through said circuit layer forming independent signal paths.

2. The method of claim 1, wherein the first and second layers are part of an integrated circuit design library of fabricated circuit layers for use in a stacked IC.

3. The method of claim 2, wherein the integrated circuit design library of fabricated circuit layers for use in a stacked IC includes designs for a plurality of different chip sizes, and the first and second layers are selected to have the same chip size.

4. The method of claim 1, wherein the first and second layers are designed independently of design of the stacked integrated circuit.

5. The method of claim 1, wherein design of the first and second layers and design of the stacked integrated circuit are unrelated.

6. The method of claim 1, comprising:

for at least one layer of the stacked integrated circuit, designing a custom design at the time of design of the stacked integrated circuit.

7. The method of claim 1, comprising bonding together the circuit layers such that no integrated circuitry surface of a circuit layer of the stacked integrated circuit is external to the stacked integrated circuit.

8. The method of claim 1, comprising:

bonding the circuit layers using an inorganic thermal diffusion bonding process;

thinning at least one circuit layer from the backside thereof; and

on the backside of the at least one circuit layer, fabricating at least one of active circuit devices, passive circuit devices and horizontal interconnections.

9. The method of claim 1, wherein at least one of the circuit layers comprises electronic circuitry.

10. The method of claim 1, wherein at least one of the circuit layers comprises optical circuitry.

11. The method of claim 1, wherein at least one of the circuit device layers comprises a MEMS device.

12. The method of claim 1, wherein at least one circuit layer is fabricated using a substrate having a plurality of barrier layers formed therein.

13. The method of claim 1, comprising performing IC device fabrication on the backside of one or more circuit layers.

14. The method of claim 13, wherein the IC devices comprise at least one of the following:

transistors, memory cells, resistors, capacitors, inductors, radio frequency antennas and horizontal interconnections.

15. The method of claim 13, wherein the IC devices comprise at least two of the following:

transistors, memory cells, resistors, capacitors, indactors, radio frequency antennas and horizontal interconnections.

16. The method of claim 13, wherein the IC devices comprise all of the following:

transistors, memory cells, resistors, capacitors, inductors, radio frequency antennas and horizontal interconnections.

17. The method of claim 1, comprising making the stacked integrated circuit without fabrication of a circuit layer specific to the function of the particular stacked integrated circuit.

18. The method of claim 1, wherein fewer than all of the circuit layers are fabricated for the specific function of the particular stacked integrated circuit.

19. The method of claim 1, wherein IC device fabrication is performed on the backside of one or more circuit layers.

20. The method of claim 1, wherein one or more the circuit layers is thinned by removing the substrate to a barrier layer comprising a thin dielectric layer.

21. The method of claim 20, wherein the thin dielectric layer thickness is less than 100 Å

.

22. The method of claim 20, wherein the thin dielectric layer thickness is less than 200 Å

.

23. The method of claim 20, wherein the thin dielectric layer thickness is in a range of 50 Å

to 500 Å

.

24. The method of claim 1, wherein a dielectric layer is deposited on the backside of one or more the circuit layers to enhance electrical isolation of an underlying semiconductor device layer.

25. The method of claim 1, wherein IC device fabrication is performed on the backside of one or more circuit layers to complete the fabrication of IC devices partially formed on the front side of the one or more circuit layers.

26. The method of claim 1, wherein IC fabrication is performed on the backside of one or more the circuit layers to fabricate one or more layer memory layers.

27. The method of claim 26, wherein the memory layers consist of at least one of MRAM, PRAM, ferroelectric or dendritic memory.

28. The method of claim 1, wherein the circuit layers are bonded using bonding layers made from two or more metal films one of which has a lower melting temperature and which will diffuse with an immediately adjacent film.

29. The method of claim 28, wherein bonding layers are diffused metal films having a higher melting point than the lower melting point metal film.

30. The method of claim 1, comprising bonding IC substrates using at least two metal films with different melting points on each surface of the substrates to be bonded wherein during or after bonding of the substrates the metal films diffuse to form one metal film with a melting point that is higher than the lower melting point of one of the original two metal films.

31. The method of claim 1, comprising bonding a plurality of circuit layers bonded using one or more bonding layers made from Sn and Al films wherein the Sn film prevents the formation of AI oxide on the Al film and diffuses into the Al film when bonded to another circuit layer.

32. The method of claim 1, comprising:

making design changes to a circuit layer;

causing the circuit layer to be fabricated; and

stacking the circuit layer together with a plurality of other previously-fabricated circuit layers;

wherein the design changes to the circuit layer do not require the other circuit layers be fabricated again.

33. The method of claim 1, wherein an application-specific function of the stacked IC is derived from the choice and quantity of circuit layers from previously-fabricated, non-application-specific circuit layers.

34. The method of claim 1, wherein interconnections of circuitry on at least one of the circuit layers are changed by interconnections on the backside of the circuit layer.

35. The method of claim 1, comprising processing both sides of an IC substrate having a frontside and a backside wherein the IC substrate is bonded face down onto a second substrate and the backside of the IC substrate is thinned to a thickness that permits conventional IC fabrication processing, further comprising forming interconnections between circuitry on the frontside of the IC substrate with the circuitry formed on the backside of the IC substrate.

36. The method of claim 1, comprising back biasing one or more transistor gates of at least one circuit layer by forming a contact on the backside of the at least one circuit layer opposite the one or more transistor gates.

37. The method of claim 1, wherein I/O drivers for the stacked IC are physically on a separate circuit layer or on the backside of one of the circuit layers.

38. The method of claim 1, comprising predominately removing dielectric in one of the circuit layers leaving free-standing metal horizontal and vertical interconnections.

39. The method of claim 1, wherein the circuit layers are provided from an inventory of substrates with completed circuitry thereon.

40. The method of claim 1, comprising aligning two substrates or wafers having circuitry thereon for bonding, wherein an opening is made from a backside of one of the substrates or wafers to be bonded to expose an alignment mark, thereby allowing the use of optical alignment methods.

41. The method of claim 1, comprising aligning two substrates or wafers with circuitry thereon for bonding, wherein an opening is made from a backside forming an opening on the front side of one of the substrates or wafers to be bonded exposing an alignment mark, and using an atomic force microscope to access alignment marks on both substrates or wafers at the same time.

42. The method of claim 1, wherein the stacked IC comprises a stacked programmable logic device having at least one of a programmable gate circuit layer and a memory circuit layer, comprising adding to the stacked programmable logic device one or more programmable gate circuit layers or memory circuit layers.

43. The method of claim 1, whererin the library is composed of a plurality of fabricated IC, stacked integrated circuit and MEMS designs designed to be used in a stacked integrated circuit.

44. The method of claim 1, whererin at least one of the circuit layers has a principle surface with active circuitry formed thereon and contacts formed on the surface opposite the principle surface.

45. The method of claim 1, wherein at least one of the following is performed:

deposition of a dielectric layer on the backside of one or more of the circuit layers to enhance electrical isolation of an underlying semiconductor device layer;

fabrication of one or more IC devices on the backside of one or more circuit layers to complete the fabrication of IC devices partially formed on the front side of the one or more circuit layers;

fabrication of IC devices on the backside of one or more circuit layers to fabricate one or more memory layers consisting of at least one or MRAM, PRAM, ferroelectric and dendritic memory.