Massively parallel interface for electronic circuit
First Claim
1. A method of testing at least one semiconductor device on a wafer, comprising the steps of:
- providing a substrate having a first side and a second side opposite said first side, said substrate further comprising electrical connections extending from said first side to probes located on and extending from said second side;
providing an interface assembly comprising at least one test electronics module electrically connected to said first side of said substrate, said test electronics modules comprising test electronics;
receiving signals at said any of said test electronics modules and said substrate;
processing at least one of said received signals within said test electronics at said test electronics modules; and
outputting said processed signals to any of said semiconductor device and said test apparatus.
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Accused Products
Abstract
Several embodiments of massively parallel interface structures are disclosed, which may be used in a wide variety of permanent or temporary applications, such as for interconnecting integrated circuits (ICs) to test and burn-in equipment, for interconnecting modules within electronic devices, for interconnecting computers and other peripheral devices within a network, or for interconnecting other electronic circuitry. Preferred embodiments of the massively parallel interface structures provide massively parallel integrated circuit test assemblies. The massively parallel interface structures preferably use one or more substrates to establish connections between one or more integrated circuits on a semiconductor wafer, and one or more test modules. One or more layers on the intermediate substrates preferably include MEMS and/or thin-film fabricated spring probes. The parallel interface assemblies provide tight signal pad pitch and compliance, and preferably enable the parallel testing or burn-in of multiple ICs, using commercial wafer probing equipment. In some preferred embodiments, the parallel interface assembly structures include separable standard electrical connector components, which reduces assembly manufacturing cost and manufacturing time. These structures and assemblies enable high speed testing in wafer form.
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Citations
27 Claims
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1. A method of testing at least one semiconductor device on a wafer, comprising the steps of:
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providing a substrate having a first side and a second side opposite said first side, said substrate further comprising electrical connections extending from said first side to probes located on and extending from said second side; providing an interface assembly comprising at least one test electronics module electrically connected to said first side of said substrate, said test electronics modules comprising test electronics; receiving signals at said any of said test electronics modules and said substrate; processing at least one of said received signals within said test electronics at said test electronics modules; and outputting said processed signals to any of said semiconductor device and said test apparatus. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
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18. A probe card assembly, comprising:
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a substrate having a first side and a second side opposite said first side, said substrate further comprising electrical connections extending from said first side to probes located on and extending from said second side for electrically contacting at least one semiconductor device; an interface assembly comprising at least one test electronics module electrically connected to said first side of said substrate; means for electrically connecting a test apparatus to any of said interface assembly and at least one of said connections on said first side of said substrate; and test electronics, at least a portion of which are disposed on said test electronics module; wherein said test electronics receive as input signals received from any of said test apparatus and said semiconductor device, process said received signals there within, and output said processed received signals. - View Dependent Claims (19, 20, 21, 22)
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23. A method of making a probe card assembly, comprising the steps of:
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providing a substrate having a first side and a second side opposite said first side, said substrate further comprising a plurality of contacts on said first side and electrical connections extending from said first side to probes located on and extending from said second side for electrically contacting at least one semiconductor device; providing an interface assembly comprising at least one test electronics module electrically connected to said first side of said substrate; and providing test electronics that receive as input signals received from any of said test apparatus and said semiconductor device, process said received signals there within, and output said processed received signals; wherein at least a portion of said test electronics are located on said test electronics module. - View Dependent Claims (24, 25, 26, 27)
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Specification