Integrated DRAM-NVRAM multi-level memory

• US 7,403,416 B2
• Filed: 03/03/2006
• Issued: 07/22/2008
• Est. Priority Date: 08/27/2004
• Status: Expired due to Fees

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Bhattacharyya, Arup, Forbes, Leonard
• Primary Examiner(s): Nguyen; Viet Q
• Application Number:
  US11/367,925
• Publication Number:
  US 20060146606A1
• Time in Patent Office: 872 Days
• Field of Search: 365/185.08, 365/185.05, 365/185.18, 365/185.24, 365/185.26, 365/189.01
• US Class Current: 365/185.08
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5671 using charge trapping in an insulator
• CPC Class Codes: G11C 14/00 Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
• CPC Class Codes: G11C 14/0018 whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor

Abstract

An integrated DRAM-NVRAM, multi-level memory cell is comprised of a vertical DRAM device with a shared vertical gate floating plate device. The floating plate device provides enhanced charge storage for the DRAM part of the cell through the shared floating body in a pillar between the two functions. The memory cell is formed in a substrate with trenches that form pillars. A vertical wordline/gate on one side of a pillar is used to control the DRAM part of the cell. A vertical trapping layer on the other side of the pillar stores one or more charges as part of the floating plate device and to enhance the DRAM function through the floating body between the DRAM and floating plate device. A vertical NVRAM wordline/control gate is formed alongside the trapping layer and is shared with an adjacent floating plate device.

Claims

1. A method for operation of an integrated DRAM-NVRAM cell, the cell comprising a DRAM gate, a NVRAM control gate, a DRAM source region, a NVRAM source region, a shared drain region, and a bitline coupled to the shared drain region, the method comprising:

applying a ground potential to the NVRAM control gate;

applying a positive bias voltage to the DRAM gate; and

applying the ground potential to the NVRAM source region wherein the DRAM is in one of a read or write operational mode in response to the positive bias voltage.

2. The method of claim 1 wherein the ground potential applied to the NVRAM control gate is shared by an adjacent NVRAM cell.

3. The method of claim 1 wherein the ground potential applied to the NVRAM control gate causes the integrated DRAM-NVRAM cell to operate as a DRAM function.

4. The method of claim 1 wherein the bitline is allowed to float.

5. The method of claim 1 wherein the bitline is biased at 2.5V.

6. The method of claim 1 and further including applying a negative substrate bias.

7. The method of claim 6 wherein the negative substrate bias is −

2.5V.

8. A method for operation of an integrated DRAM-NVRAM cell in a vertical pillar, the cell comprising a vertical DRAM gate, a vertical NVRAM control gate, a DRAM source region, a NVRAM source region, a shared drain region, and a bitline coupled to the shared drain region, the method comprising:

applying a ground potential to the vertical NVRAM control gate;

applying a voltage to the vertical DRAM gate; and

applying a ground potential to the NVRAM source region wherein the DRAM is in one of a read or write operational mode in response to the voltage.

9. The method of claim 8 wherein during operation a floating body forms in the pillar.

10. The method of claim 9 wherein the floating body forms in response to depletion regions forming around each source region.

11. The method of claim 10 wherein the floating body forms between the shared drain region and the DRAM and NVRAM depletion regions.

12. The method of claim 8 wherein a channel region exists between the shared drain region and the NVRAM source region.

13. The method of claim 8 wherein a channel region exists between the shared drain region and the DRAM source region.

14. The method of claim 12 wherein a channel forms in the channel region in response to biasing of the NVRAM.

15. The method of claim 13 wherein a channel forms in the channel region in response to biasing of the DRAM.

16. A method for operation of an integrated DRAM-NVRAM cell in a vertical pillar, the cell comprising a vertical DRAM gate on a first pillar side, a vertical NVRAM control gate on a second pillar side, a DRAM source region under a first trench, a NVRAM source region under a second trench, a shared drain region at the top of the pillar, and a bitline coupled to the shared drain region, the method comprising:

applying 0V to the vertical NVRAM control gate;

applying a positive voltage to the vertical DRAM gate; and

applying 0V to the NVRAM source region wherein the DRAM is in one of a read or write operational mode in response to the level of the positive voltage.

17. The method of claim 16 wherein the bitline is floating.

18. The method of claim 16 wherein the DRAM function operates as an access device for the NVRAM function.