Systems for erasing non-volatile memory utilizing changing word line conditions to compensate for slower erasing memory cells

• US 7,403,428 B2
• Filed: 12/06/2005
• Issued: 07/22/2008
• Est. Priority Date: 03/31/2005
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Higashitani, Masaaki
• Primary Examiner(s): Nguyen; Viet Q.
• Application Number:
  US11/296,032
• Publication Number:
  US 20060221703A1
• Time in Patent Office: 959 Days
• Field of Search: 365/185.29, 365/185.18, 365/185.17, 365/185.24, 365/185.33
• US Class Current: 365/185.29
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/3404 Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
• CPC Class Codes: G11C 16/3409 Circuits or methods to recover overerased nonvolatile memory cells detected during erase verification, usually by means of a "soft" programming step
• CPC Class Codes: G11C 16/345 Circuits or methods to detect overerased nonvolatile memory cells, usually during erasure verification
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 16/3468 Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing
• CPC Class Codes: G11C 16/3472 Circuits or methods to verify correct erasure of nonvolatile memory cells whilst erasing is in progress, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate erasure
• CPC Class Codes: G11C 16/3477 Circuits or methods to prevent overerasing of nonvolatile memory cells, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate erasing
• CPC Class Codes: G11C 2211/5621 Multilevel programming verification
• CPC Class Codes: G11C 2216/18 Flash erasure of all the cells in an array, sector or block simultaneously

Abstract

Voltage conditions applied to the memory cells of a non-volatile memory system are changed during erase operations in order to equalize the erase behavior of the select memory cells with other memory cells of the system that are being concurrently erased. The changed conditions can compensate for capacitively coupled voltages within a NAND string. After biasing a NAND string for an erase operation and beginning application of the erase voltage pulse, the word lines of one or more interior memory cells can be floated. By floating the selected interior word lines, the peak erase potential created across the tunnel dielectric region of the cells coupled thereto is decreased from its normal level. Consequently, the erase rates of these cells are slowed to substantially match that of the slower erasing end memory cells of the string. Different word lines can be floated at different times to alter the erase behavior of different memory cells by different amounts.

Claims

1. A non-volatile memory system, comprising:

a set of non-volatile storage elements having a well region, said set includes a first and a second subset of non-volatile storage elements, said first subset is interior to said second subset;

said set of non-volatile storage elements includes a first non-volatile storage element adjacent to a first select gate for said set and a second non-volatile storage element adjacent to a second select gate for said set;

said second subset of non-volatile storage elements is interior with respect to said first non-volatile storage element and said second non-volatile storage element; and

managing circuitry in communication with said set of non-volatile storage elements, said managing circuitry receives a request to erase said set, said managing circuitry, in response to said request, applies a first voltage signal to each non-volatile storage element in said set, applies an erase voltage to said well region, and changes said first voltage signal for each non-volatile storage element in said first subset after beginning application of said erase voltage, said managing circuitry changes said first voltage signal while applying said erase voltage to said well region, said managing circuitry changes said first voltage signal for each non-volatile storage element in said second subset after changing said first voltage signal for each non-volatile storage element in said first subset.

2. The non-volatile memory system of claim 1, wherein:

said managing circuitry changes said first voltage signal for each non-volatile storage element in said first subset by floating a control gate of each non-volatile storage element in said first subset.

3. The non-volatile memory system of claim 2, wherein:

said erase voltage is an erase voltage pulse having a peak value; and

said managing circuitry begins floating a control gate of each non-volatile storage element in said first subset prior to said erase voltage pulse reaching said peak value;

said first voltage signal comprises a first voltage applied to each non-volatile storage element in said set by said managing circuitry; and

said managing circuitry reapplies said first voltage to said first subset of non-volatile storage elements after floating said control gate of each non-volatile storage element in said first subset, said managing circuitry reapplies said first voltage while said erase voltage pulse is still being applied to said well region and after said erase voltage pulse reaches said peak value.

4. The non-volatile memory system of claim 1, wherein:

said managing circuitry changes said first voltage signal by providing a single change to said first voltage signal for each non-volatile storage element in said first subset.

5. The non-volatile memory system of claim 1, wherein:

said set of non-volatile storage elements is a NAND string of multi-state flash memory devices;

said set of multi-state flash memory devices is part of an array of multi-state flash memory devices;

said array is in communication with a host system; and

said array is removable from said host system.

6. The non-volatile memory system of claim 1, wherein said managing circuitry transfers charge from a floating gate of each non-volatile storage element in said set of non-volatile storage elements while applying said erase voltage to said well region.

7. A non-volatile memory system, comprising:

a set of non-volatile storage elements having a well region, said set includes a first and a second subset of non-volatile storage elements, said first subset is interior to said second subset;

managing circuitry in communication with said set of non-volatile storage elements, said managing circuitry receives a request to erase said set, said managing circuitry, in response to said request, applies a first voltage signal to each non-volatile storage element in said set, applies an erase voltage to said well region, and changes said first voltage signal for each non-volatile storage element in said first subset after beginning application of said erase voltage, said managing circuitry changes said first voltage signal by floating a control gate of each non-volatile storage element in said first subset while applying said erase voltage to said well region.

8. The non-volatile memory system of claim 7, wherein:

said set non-volatile storage elements is coupled to a set of word lines;

said first subset of non-volatile storage elements is coupled to a first subset of word lines;

said second subset of non-volatile storage elements is coupled to a second subset of word lines; and

said managing circuitry floats a control gate of each non-volatile storage element in said first subset by floating said first subset of word lines.

9. The non-volatile memory system of claim 7, wherein:

said managing circuitry applies a first voltage to a control gate of each non-volatile storage element in said set prior to floating a control gate of each non-volatile storage element in said first subset of non-volatile storage elements, said managing circuitry applies said first voltage while applying said erase voltage.

10. The non-volatile memory system of claim 9, wherein:

said erase voltage is an erase voltage pulse having a peak value; and

said managing circuitry floats a control gate of each non-volatile storage element in said first subset prior to said erase voltage pulse reaching said peak value.

11. The non-volatile memory system of claim 9, wherein:

said managing circuitry reapplies said first voltage to said control gate of each non-volatile storage element in said first subset, said managing circuitry begins reapplying said first voltage while said erase voltage pulse is being applied to said well region.

12. The non-volatile memory system of claim 11, wherein:

said managing circuitry begins reapplying said first voltage after said erase voltage pulse begins decreasing from said peak value.

13. The non-volatile memory system of claim 7, wherein:

said managing circuitry causes a first potential to exist between a floating gate of each non-volatile storage element in said second subset and said well region by applying said erase voltage and applying said first voltage; and

said managing circuitry causes a second potential to exist between a floating gate of each non-volatile storage element in said first subset and said well region by applying said erase voltage, applying said first voltage, and floating said control gate of each non-volatile storage element in said first subset, said first potential is substantially equal to said second potential.

14. The non-volatile memory system of claim 7, wherein:

said non-volatile storage elements of said set are coupled together in series and include a first non-volatile storage element adjacent to a first select gate for said set and a second non-volatile storage element adjacent to a second select gate for said set;

said second subset of non-volatile storage elements is interior with respect to said first non-volatile storage element and said second non-volatile storage element; and

said managing circuitry floats a control gate of each non-volatile storage element in said second subset after beginning application of said erase voltage and while still applying said erase voltage, said managing circuitry begins floating said control gate of each non-volatile storage element in said second subset after beginning to float said control gate of each non-volatile storage element in said first subset.

15. The non-volatile memory system of claim 7, wherein:

said managing circuitry floats said control gate of each non-volatile storage element in said first subset by providing no electrical connection to said control gate of each non-volatile storage element in said first subset.

16. The non-volatile memory system of claim 7, wherein:

said set of non-volatile storage elements is part of an array of non-volatile storage elements;

said array is in communication with a host system;

said array is removable from said host system; and

said managing circuitry includes at least one of a controller, a state machine, and a row controller.

17. A non-volatile memory system, comprising:

a set of non-volatile storage elements having a well region, said set includes a first and a second subset of non-volatile storage elements, said first subset is interior to said second subset;

a set of word lines coupled to said set of non-volatile storage elements, said set includes a first subset of word lines in communication with said first subset of non-volatile storage elements and a second subset of word lines in communication with said second subset of non-volatile storage elements; and

managing circuitry in communication with said set of non-volatile storage elements, said managing circuitry receives a request to erase said set, said managing circuitry, in response to said request, applies a first voltage signal to each non-volatile storage element in said set, applies an erase voltage to said well region, and changes said first voltage signal for each non-volatile storage element in said first subset after beginning application of said erase voltage and while still applying said erase voltage, said managing circuitry enforces a first voltage condition on said set of word lines as part of applying said first voltage signal and stops enforcement of said first voltage condition on said first subset of word lines to change said first voltage signal for each non-volatile storage element in said first subset while continuing to enforce said first voltage condition on said second subset of word lines.

18. The method of claim 17, wherein:

said managing circuitry stops enforcement of said first voltage condition by floating each word line in said first subset of word lines.

19. The non-volatile memory system of claim 17, wherein:

said erase voltage is an erase voltage pulse having a peak value;

said managing circuitry stops enforcement of said first voltage condition prior to said erase voltage pulse reaching said peak value;

said managing circuitry enforces said first voltage condition on said set of word lines by applying a first voltage to each word line in said set; and

said managing circuitry reapplies said first voltage to said first subset of word lines after said erase voltage pulse reaches said peak value, said managing circuitry begins reapplying said first voltage while said erase voltage pulse is being applied to said well region and after stopping enforcement of said first voltage condition.

20. The non-volatile memory system of claim 17, wherein:

said set of non-volatile storage elements includes a third subset of non-volatile storage elements, said first subset of non-volatile storage elements is interior to said third subset of non-volatile storage elements;

said set of word lines includes a third subset of word lines in communication with said third subset of non-volatile storage elements;

said managing circuitry stops enforcement of said first voltage condition on said third subset of word lines to change said first voltage signal for each non-volatile storage element in said third subset, said managing circuitry stops enforcement of said first voltage condition on said third subset of word lines after stopping enforcement of said first voltage condition on said first subset of word lines; and

said managing circuitry continues to enforce said first voltage condition on each word line of said set that is not in said first subset or said third subset after stopping enforcement of said first voltage condition on said first subset and said third subset of word lines.

21. The non-volatile memory system of claim 17, wherein:

said set of non-volatile storage elements is a NAND string of flash memory cells.