Multicast and broadcast operations in ethernet switches

• US 7,403,521 B2
• Filed: 12/03/2001
• Issued: 07/22/2008
• Est. Priority Date: 12/03/2001
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Saxena, Rahul
• Primary Examiner(s): Vu, Huy D.
• Assistant Examiner(s): MATTIS, JASON E
• Application Number:
  US10/004,765
• Publication Number:
  US 20030103517A1
• Time in Patent Office: 2,423 Days
• Field of Search: 370/230, 370389-390, 370/392, 370/400, 370412-414, 370419-421, 370422-423, 370428-429, 370431-432
• US Class Current: 370/390
• CPC Class Codes: H04L 49/201 Multicast operation; Broadcast operation
• CPC Class Codes: H04L 49/252 Store and forward routing
• CPC Class Codes: H04L 49/254 Centralised controller, i.e. arbitration or scheduling
• CPC Class Codes: H04L 49/351 for local area network [LAN], e.g. Ethernet switches

Abstract

A switch and a process of operating a switch are described where a received data frame is copied one or more times into a memory before being transmitted out of the switch. The switch and method determine how much space in the memory is needed to store all of the copies of the received data frame and then the switch and method determine locations in the memory for storing the copies of the received data frames. The copies of the received data frame are stored until the ports designated as transmitting the copies of the received data frame are ready. When a port is ready, a copy of the received data frame is read out of the memory and the port is instructed where to locate the copy on a bus. When the port has retrieved the copy of the data frame, it transmits the data frame out of the switch.

Claims

1. A switching apparatus comprising:

a first port coupled to receive an input data frame;

a first logic circuit coupled to receive the input data frame from the first port and configured to determine a number of copies of the input data frame to make and to make the number of copies of the input data frame;

a first memory comprising multiple segments, each segment comprising multiple independently addressable channels, the first logic circuit configured to determine a number of channels and segments needed to store the number of copies of the input data frame, the first memory coupled to the first logic circuit and configured to store multiple copies of the input data frame within a single segment of the determined number of segments and to read the multiple copies of the input data frame from the single segment in a single read cycle; and

multiple transmitting ports coupled to the first memory and configured to receive copies of the input data frame from the first memory in parallel and to simultaneously transmit the copies of the input data frame, each of the multiple transmitting ports associated with an output control logic circuit coupled to the first memory and configured to determine when to read at least one copy of the input data frame from the first memory;

wherein the first logic circuit further comprises a third logic circuit configured to determine one or more empty locations in the first memory to store the copies of the input data frame.

2. The switching apparatus of claim 1 wherein the first logic circuit further comprises a second memory configured to keep track of all of the empty locations in the first memory.

3. The switching apparatus of claim 2 wherein:

the third logic circuit is configured to determine where there are empty channels in the first memory to store the copies of the input data frame.

4. The switching apparatus of claim 2 wherein:

the third logic circuit is configured to determine where there is at least one empty segment in the first memory to store one of the copies of the input data frame.

5. The switching apparatus of claim 1 wherein:

the third logic circuit is configured to determine how many additional ports will output some of the copies of the input data frame and to calculate the minimum amount of storage space that is necessary to store all of the necessary copies of the input data frame in the first memory.

6. The switching apparatus of claim 1 wherein the first logic circuit further comprises a fourth logic circuit configured to determine the size of the input data frame such that the size of the input data frame is used to calculate the minimum amount of storage space necessary to store the copies of the input data frame.

7. The switching apparatus of claim 1 wherein the first memory is distributed across the switching apparatus.

8. The switching apparatus of claim 1 further comprising a bus coupled with the first memory and one or more transmitting ports and configured to transmit data including at least one copy of the input data frame from the first memory to the one or more transmitting ports.

9. The switching apparatus of claim 8 wherein one or more transmitting ports comprises a logic circuit configured to select the at least one copy of the input data frame from the bus.

10. The switching apparatus of claim 1 wherein at least one output control logic circuit is further configured to indicate a location in the first memory where an associated transmitting port is to obtain the at least one data frame for transmitting.

11. A switching apparatus comprising:

a first logic circuit coupled to receive an input data frame and configured to determine a number of copies of the input data frame to make and to make the determined number of copies of the input data frame;

a memory coupled to the first logic circuit and configured to store and read the copies of the input data frame, the memory being comprised of segments including independently addressable channels with one or more segments being accessible at a given time, the first logic circuit configured to determine a number of channels and segments needed to store the number of copies of the input data frame, the first memory to store multiple copies of the input data frame within a single segment of the determined number of segments and to read the multiple copies of the input data frame from the single segment in a single read cycle; and

multiple transmitting ports coupled to the first memory and configured to receive copies of the input data frame from the first memory in parallel and to simultaneously transmit the copies of the input data frame, each of the multiple transmitting ports associated with an output control logic circuit coupled to the memory and configured to determine when to read at least one copy of the input data frame from the memory;

wherein the first logic circuit further comprises a third logic circuit configured to determine one or more empty locations in the memory to store the copies of the input data frame.

12. The switching apparatus of claim 11 wherein the third logic circuit is configured to determine where there are empty channels in the memory for storing copies of the input data frame.

13. The switching apparatus of claim 11 wherein the third logic circuit is configured to determine where there is at least one empty segment in the memory for storing at least one copy of the input data frame.

14. The switching apparatus of claim 11 wherein the third logic circuit is configured to determine how many of the multiple transmitting ports will output some of the number of copies of the input data frame and to calculate the minimum amount of storage space necessary to store all of the necessary copies of the input data frame in the memory.

15. The switching apparatus of claim 11 wherein the first logic circuit further comprises a fourth logic circuit configured to determine the size of the input data frame in calculating the minimum amount of storage space to store the necessary copies of the input data frame in the memory.

16. A switching apparatus comprising:

a first port coupled to receive an input data frame;

a memory coupled to the first port and configured to store and read a number of copies of the input data frame, the memory comprising multiple segments, each segment comprising multiple independently addressable channels;

a processor coupled to the memory and programmed to determine the number of copies of the input data frame to make and to determine when to read at least one copy of the input data frame from the memory, the processor configured to determine a number of channels and segments needed to store the number of copies of the input data frame, the memory to store multiple copies of the input data frame within a single segment of the determined number of segments and to read the multiple copies of the input data frame from the single segment in a single read cycle; and

multiple transmitting ports coupled to the memory and configured to receive copies of the input data frame from the first memory in parallel and to simultaneously transmit the copies of the input data frame after being read from the memory;

wherein the processor is configured to determine one or more empty locations in the memory to store the copies of the input data frame.

17. The switching apparatus of claim 16 wherein the processor determines where there are empty channels in the memory to store the number of copies of the input data frame.

18. The switching apparatus of claim 16 wherein the processor determines where there is at least one empty segment in the memory to store the number of copies of the input data frame.

19. The switching apparatus of claim 16 wherein the processor determines how many transmitting ports will output any of the copies of the data frame and calculates a minimum amount of storage space necessary to store the copies of the input data frame.

20. The switching apparatus of claim 19 wherein the processor determines the size of the input data frame and uses this determination in calculating the minimum amount of storage space to store the number of copies of the input data frame.

21. A computer readable medium for use in a switching apparatus that includes a processor, the computer readable medium including instructions for causing the processor to:

determine a number of ports a received data frame is to be transmitted out over so as to generate a same number of copies of the received data frame;

determine particular locations in a memory that can store the copies of the received data frame;

determine a number of channels and segments needed to store the number of copies of the input data frame;

forward instructions and the copies of the received data frame to the memory so as to cause the memory to store multiple copies of the received data frame within a single segment of the determined number of segments;

forward instructions to the memory to read out the multiple copies of the received data frame from the single segment in parallel and output the copies onto a bus in a single clock cycle;

forward instructions to multiple transmitting ports causing the multiple transmitting ports to retrieve and simultaneously transmit the copies of the received data frame from the bus; and

determine one or more empty locations in the memory to store the copies of the input data frame.

22. The computer readable medium of claim 21 wherein the processor is instructed to determine the location or locations, addressable by channels and segments, that can store the copies of the received data frame.

23. The computer readable medium of claim 22 further comprising an instruction for the memory to store some copies of the received data frame in multiple segments of the memory.

24. The computer readable medium of claim 22 wherein when the memory reads out at least one copy of the number of copies of the received data frame, the memory also reads out a previously stored copy from a previously received data frame.

25. The computer readable medium of claim 21 wherein the instructions cause the processor to determine the size of the received data frame and use a result from this determination when the processor is determining particular locations in the memory to store the copies of the received data frame.