Systems and methods for receiving data in a wireless communication network

• US 7,403,576 B2
• Filed: 03/26/2004
• Issued: 07/22/2008
• Est. Priority Date: 12/06/2001
• Status: Expired due to Term

• Current Assignee: Intellectual Ventures Holding 81 LLC (Intellectual Ventures LLC)
• Original Assignee: Pulse-Link Incorporated
• Inventors: Lakkis, Ismail
• Primary Examiner(s): KIM, KEVIN
• Application Number:
  US10/810,410
• Publication Number:
  US 20050152475A1
• Time in Patent Office: 1,579 Days
• Field of Search: 375/316, 375/317, 375/244, 375/247, 375/252, 341/143
• US Class Current: 375/316
• CPC Class Codes: H04B 1/71637 Receiver aspects H04B1/7183 takes precedence

Abstract

A method of communicating over a wideband communication channel divided into a plurality of sub-channels comprises dividing a single serial message intended for one of the plurality of communication devices into a plurality of parallel messages, encoding each of the plurality of parallel messages onto at least some of the plurality of sub-channels, and transmitting the encoded plurality of parallel messages to the communication device over the wideband communication channel.

Claims

1. A radio receiver, comprising:

a band pass filter configured to filter a combined signal;

a clocked comparator coupled with the band pass filter, the clocked comparator configured to compare the filter combined signal to a ground reference when the comparator is enabled by a clock signal;

a digital-to-analog converter coupled with the clocked comparator, the digital-to-analog converter configured to convert the output of the clocked comparator to an analog signal; and

a combiner configured to receive a RF signal and combine the RF signal with the analog signal generated by the digital-to-analog converter in order to generate the combined signal; and

a plurality of clocked comparators coupled to the band pass filter, each of the clocked comparators configured to be activated on a different phase of a clock signal and a combiner coupled to the plurality of clocked comparators, the combiner configured to combine the outputs of the clocked comparators.

2. The radio receiver of claim 1, further comprising filtering and decimation circuitry configured to filter and decimate the output of the clocked comparator.

3. The radio receiver of claim 1, further comprising a clock signal configured to clock the clocked comparator at a rate required to achieve a selected effective number of bits at the output of the filtering and decimation circuitry.

4. The radio receiver of claim 1, wherein the combiner is a passive combiner.

5. The radio receiver of claim 1, wherein the digital-to-analog converter is coupled to the plurality of clocked comparators via the combiner.

6. A receiver, comprising:

an antenna configured to receive a RF signal;

a filter coupled to the antenna, the filter configured to filter the received RF signal;

an amplifier coupled with the filter, the amplifier configured to amplify the filtered RF signal; and

a radio receiver, comprising;

a band pass filter configured to filter a combined signal;

a plurality of clocked comparators coupled with the band pass filter, the clocked comparators configured to compare the filter combined signal to a ground reference when each comparator is enabled by a clock signal, and wherein each of the clocked comparators is configured to be activated on a different phase of the clock signal;

a combiner coupled to the plurality of clocked comparators, the combiner configured to combine the outputs of the clocked comparators;

a digital-to-analog converter coupled with the clocked comparators), the digital-to-analog converter configured to convert the output of the clocked comparators to an analog signal; and

a combiner configured to receive the amplified and filtered RF signal and combine the amplified and filtered RF signal with the analog signal generated by the digital-to-analog converter in order to generate the combined signal.

7. The receiver of claim 6, wherein the radio receiver further comprises filtering and decimation circuitry configured to filter and decimate the output of the clocked comparator.

8. The receiver of claim 6, wherein the radio receiver further comprises a clock signal configured to clock the clocked comparator at a rate required to achieve a selected effective number of bits at the output of the filtering and decimation circuitry.

9. The receiver of claim 6, wherein the combiner is a passive combiner.

10. The receiver of claim 6, wherein the digital-to-analog converter is coupled to the plurality of clocked comparators via the combiner.