System and method for predictive synchronization for locating interleaving frames and demodulation training sequences

• US 7,403,583 B1
• Filed: 02/19/2003
• Issued: 07/22/2008
• Est. Priority Date: 02/19/2003
• Status: Expired due to Fees

• Current Assignee: L-3 Communications Corporation (L3Harris Technologies, Inc.)
• Original Assignee: L-3 Communications Corporation (L3Harris Technologies, Inc.)
• Inventors: Bagley, Zachary C., Mower, Vaughn L., Bruening, Kent R.
• Primary Examiner(s): Fan; Chieh M.
• Assistant Examiner(s): Lee; Siu M
• Application Number:
  US10/369,229
• Time in Patent Office: 1,980 Days
• Field of Search: 375/130, 375/136, 375/140, 375/145, 375/147, 375/149, 375/316, 375/354, 375/367, 375/369, 370/320, 370/335, 370/342, 370/441
• US Class Current: 375/367
• CPC Class Codes: H04B 1/7075 with code phase acquisition

Abstract

A system and method for using Psuedo-Noise (PN) phase to determine frame start of a data frame is provided. The system and method includes at least two PN component codes, wherein the at least two PN component codes are relatively prime. A received PN composite encoded signal is correlated with at least one of the PN component codes and a frame start is determined. With reference to frame start at least one training sequence bit is located. The training bits may be overwritten on FEC encoded frame data such that a FEC decoder may be used to recover data overwritten by the training sequence bit(s).

Claims

1. A receiver system for determining frame start, the receiver system comprising:

a receiver, the receiver adapted to receive signals from a transmitter, the receiver comprising;

at least two receiver pseudo-noise (PN) component code generators, wherein the at least two PN component code generators are adapted to generate at least two relatively prime PN component codes, respectively; and

a frame counter, wherein the frame counter is adapted to locate frame start according to a minor PN code epoch of at least one of the at least two relatively prime PN component codes.

2. A receiver system as in claim 1 wherein the frame counter is an interleaver frame counter.

3. A receiver system as in claim 2 further comprising a training sequence locator coupled to the frame counter.

4. A receiver system as in claim 1 wherein the receiver system further comprises a receiver logic combiner coupled to the at least two receiver PN component code generators, the receiver logic combiner adapted to generate at least one composite PN code;

at least one marker signal; and

at least one resync signal.

5. A receiver system as in claim 4 wherein the at least one marker signal comprises at least one minor PN code epoch, wherein the at least one minor PN code epoch comprises an all ones state of at least one of the relatively prime PN component codes.

6. A receiver system as in claim 4 wherein the at least one resync signal comprises a PN major epoch, wherein the PN major epoch comprises an all ones state of at least two of the relatively prime PN component codes.

7. A receiver system as in claim 4, where the logic combiner comprises one of a MAND logic combiner, a MAJ logic combiner and a MOD logic combiner.

8. A receiver system as in claim 4, further comprising a forward error correction (FEC) decoder coupled to a training sequence locator.

9. A receiver system as in claim 8, where said FEC decoder corrects data overwritten by at least one training bit.

10. A method for using Psuedo-Noise (PN) phase to determine frame start of a data frame, the method comprising:

providing at least two PN component codes, wherein the at least two PN component codes are relatively prime;

correlating a received PN composite encoded signal with at least one of the PN component codes; and

determining a frame start in accordance with a minor PN code epoch of at least one of the PN component codes correlated with the received PN composite encoded signal.

11. A method as in claim 10 wherein determining the frame start in accordance with the at least one of the PN component codes correlated with the received PN composite encoded signal further comprises:

determining at least one PN code epoch; and

generating a start-of-frame marker in accordance with determining the at least one PN epoch.

12. A method as in claim 11 wherein determining the at least one PN epoch further comprises determining at least one minor PN code epoch.

13. A method as in claim 11 wherein determining the at least one PN epoch further comprises determining at least one PN code major epoch.

14. A method as in claim 11 wherein generating the start-of-frame marker further comprises generating a start-of-interleaver-frame marker.

15. A method for using Psuedo-Noise (PN) phase to determine frame start of a data frame, the method comprising:

providing at least two PN component codes, wherein the at least two PN component codes are relatively prime;

correlating a received PN composite encoded signal with at least one of the PN component codes; and

determining a frame start in accordance with the at least one of the PN component codes correlated with the received PN composite encoded signal further comprising;

determining at least one PN code epoch;

generating a start-of-frame marker in accordance with determining the at least one PN epoch; and

locating at least one training sequence bit in accordance with generating the start-of-frame marker.

16. A method for using Psuedo-Noise (PN) phase to determine frame start of a data frame, the method comprising:

providing at least two PN component codes, wherein the at least two PN component codes are relatively prime;

correlating a received PN composite encoded signal with at least one of the PN component codes; and

determining a frame start in accordance with the at least one of the PN component codes correlated

with the received PN composite encoded signal further comprising;

determining at least one PN code epoch;

generating a start-of-frame marker in accordance with determining the at least one PN epoch;

locating at least one training sequence bit in accordance with generating the start-of-frame marker; and

forward error correction (FEC) decoding the data frame to recover data overwritten by the at least one training sequence bit.

17. An integrated circuit (IC), wherein the IC comprises:

at least two receiver pseudo-noise (PN) component code generators, wherein the at least two PN component code generators are adapted to generate at least two relatively prime PN component codes, respectively; and

a frame counter, wherein the frame counter is adapted to locate frame start according to a minor PN code epoch of at least one of the at least two receiver PN component code generators.

18. An IC as in claim 17 wherein the IC further comprises a receiver logic combiner adapted to generate a receiver composite PN code.

19. An IC as in claim 18, where the logic combiner comprises one of a MAND logic combiner, a MAJ logic combiner and a MOD logic combiner.

20. An IC as in claim 17, where the IC comprises an Application Specific IC (ASIC).

21. An IC as in claim 17, where the IC comprises a field programmable gate array (FPGA).

22. A storage device tangibly embodying a program of instructions, readable by a machine, and executable by the machine to perform method steps for using Psuedo-Noise (PN) phase to determine frame start of a data frame, the method comprising:

providing at least two PN component codes, wherein the at least two PN component codes are relatively prime;

correlating a received PN composite encoded signal with at least one of the PN component codes;

determining a frame start in accordance with a minor PN code epoch of the at least one of the PN component codes correlated with the received PN composite encoded signal;

locating at least one training sequence bit in accordance with determining the frame start; and

forward error correction (FEC) decoding the data frame to recover data overwritten by the at least one training sequence bit.

23. The storage device tangibly embodying the program of instructions executable by the machine as in claim 22, where the program of instructions comprise at least one Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL) file.