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Self-synchronising bit error analyser and circuit

  • US 7,404,115 B2
  • Filed: 12/01/2005
  • Issued: 07/22/2008
  • Est. Priority Date: 02/12/2004
  • Status: Expired due to Fees
First Claim
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1. A method of synchronising a generator LFSR and a receiver LFSR in a data bus analyser comprising the steps of:

  • (a) selecting a sample of data generated by the generator LFSR;

    (b) transmitting the sample through a data bus;

    (c) selecting a sample of data generated by the receiver LFSR;

    (d) comparing the sample of data from the generator LFSR with the sample of data from the receiver LFSR;

    (e) adjusting the receiver LFSR based on step (d); and

    (f) repeating steps (a) to (e) until the sample of data from the receiver LFSR is substantially the same as the sample of data from the generator LFSR.

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