Self-synchronising bit error analyser and circuit

• US 7,404,115 B2
• Filed: 12/01/2005
• Issued: 07/22/2008
• Est. Priority Date: 02/12/2004
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Pereira, David, Malcavet, Didier, Steimle, Andre, Boudon, Gerard
• Primary Examiner(s): Trimmings; John P
• Application Number:
  US11/164,690
• Publication Number:
  US 20070011534A1
• Time in Patent Office: 964 Days
• Field of Search: None
• US Class Current: 714/715
• CPC Class Codes: G01R 31/3171 BER [Bit Error Rate] test

Abstract

A self-synchronising data bus analyser comprising a generator LFSR, a receiver LFSR and a comparator

• wherein the generator LFSR generates a first data set which is transmitted through a data bus to the comparator; and
• wherein the comparator compares the first data set with a second data set generated by the receiver LFSR and adjusts the receiver LFSR until the second data set is substantially the same as the first data set.

Claims

1. A method of synchronising a generator LFSR and a receiver LFSR in a data bus analyser comprising the steps of:

(a) selecting a sample of data generated by the generator LFSR;

(b) transmitting the sample through a data bus;

(c) selecting a sample of data generated by the receiver LFSR;

(d) comparing the sample of data from the generator LFSR with the sample of data from the receiver LFSR;

(e) adjusting the receiver LFSR based on step (d); and

(f) repeating steps (a) to (e) until the sample of data from the receiver LFSR is substantially the same as the sample of data from the generator LFSR.

2. The method of synchronising a generator LFSR and a receiver LFSR in a data bus analyser as claimed in claim 1 wherein the step (e) of adjusting the receiver LFSR comprises right shifting the receiver LFSR.

3. The method of synchronising a generator LFSR and a receiver LFSR in a data bus analyser as claimed in claim 1 wherein the method is preceded by a step of initialising the receiver LFSR with a sample of data generated by the generator LFSR.

4. The method of synchronising a generator LFSR and a receiver LFSR in a data bus analyser as claimed in claim 1 wherein step (f) is a followed by a verification procedure in the event that the sample of data from the receiver LFSR substantially matches the sample of data from generator LFSR and wherein the verification procedure comprises the steps of:

(g) selecting a further sample of data generated by the generator LFSR;

(h) transmitting the further sample through the data bus;

(i) selecting a further sample of data generated by the receiver LFSR;

(j) comparing the further sample of data generated by the generator LFSR with the further sample of data generated by the receiver LFSR; and

(k) restarting steps (a) to (f) of the method of synchronising the generator LFSR with the receiver LFSR in the event that the further sample of data from the receiver LFSR does not substantially match the further sample of data from the generator LFSR.