Memory error analysis for determining potentially faulty memory components
First Claim
1. A computer system comprising a plurality of memory components where bits are distributed among a plurality of the memory components and an error analyzer operable to, for an uncorrectable multiple bit error, identify a memory component as potentially faulty by using generated syndromes to access a table operable to map syndromes to memory components, wherein the syndromes are generated using bits of an error correction code, wherein the error correction code is a SEC-DED-S4ED code.
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Accused Products
Abstract
Accordingly, there has been described a computer system with a plurality of memory components where individual bits from multiple words are distributed among the memory components. An error analyzer is operable to identify a memory component as potentially faulty by accessing a table mapping syndromes to memory components using generated syndromes.
33 Citations
28 Claims
- 1. A computer system comprising a plurality of memory components where bits are distributed among a plurality of the memory components and an error analyzer operable to, for an uncorrectable multiple bit error, identify a memory component as potentially faulty by using generated syndromes to access a table operable to map syndromes to memory components, wherein the syndromes are generated using bits of an error correction code, wherein the error correction code is a SEC-DED-S4ED code.
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3. A computer system comprising:
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a plurality of memory components, wherein bits from a group of bits that comprises one or more words are stored distributed between memory components, the group of bits comprising data bits and error correction code bits, wherein the error correction code is a SEC-DED-S4ED code; a syndrome generator, operable to generate a syndrome from regenerated error correction code bits for the group of bits and stored error correction code bits for the stored group of bits; a table comprising entries linking syndromes to memory components; and an error analyzer operable to, for an uncorrectable multiple bit error, identify a memory component as potentially faulty by accessing the table using a generated syndrome. - View Dependent Claims (4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A method of identifying a faulty memory component in a computer system, the method comprising:
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generating a syndrome from regenerated error correction code bits for a group of bits and stored error correction code bits for a stored group of bits, wherein bits from the group of bits, which comprises data bits and error correction code bits in one or more words, are distributed between memory components, wherein the error correction code is a SEC-DED-S4ED code; and for an uncorrectable multiple bit error, identifying a memory component as potentially faulty by accessing a table comprising entries linking syndromes to memory components using a generated syndrome. - View Dependent Claims (17, 18, 19, 20, 21, 22, 23, 24, 25, 26)
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27. A computer system comprising:
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memory means for storing bits from a group of bits that comprises one or more words, wherein individual bits from the group of bits are stored distributed between memory components, said group of bits comprising data bits and error correction code bits, wherein the error correction code is a SEC-DED-S4ED code; a syndrome means for generating a syndrome from regenerated error correction code bits for a said group of bits and stored error correction code bits for said stored group of bits; and table means for entries linking syndromes to memory components; and error analysis means for identifying a memory component, for an uncorrectable multiple bit error, as potentially faulty by accessing the table using a generated syndrome.
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28. A computer program product comprising program code operable to perform the steps of:
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generating a syndrome from regenerated error correction code bits for a group of bits and stored error correction code bits for a stored group of bits, wherein individual bits from the group of bits, which comprises comprising data bits and error correction code bits in one or more words, is distributed between memory components, wherein the error correction code is a SEC-DED-S4ED code; and for an uncorrectable multiple bit error, identifying a memory component as potentially faulty by accessing a table comprising entries linking syndromes to memory components using a generated syndrome.
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Specification