Inspection method and inspection apparatus for semiconductor integrated circuit

• US 7,404,158 B2
• Filed: 10/17/2005
• Issued: 07/22/2008
• Est. Priority Date: 10/19/2004
• Status: Expired due to Fees

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Nakajima, Yukinori
• Primary Examiner(s): Siek; Vuthe
• Assistant Examiner(s): Sandoval; Patrick
• Application Number:
  US11/250,377
• Publication Number:
  US 20060090147A1
• Time in Patent Office: 1,009 Days
• Field of Search: 716/1, 716/4, 716/5, 716/6, 702/117, 714/724, 714/725, 324/765, 324/766, 324/158.1
• US Class Current: 716/136
• CPC Class Codes: G01R 31/318357 Simulation computer simulation of digital circuits G06F30/3308
• CPC Class Codes: G06F 11/261 by simulating additional hardware, e.g. fault simulation

Abstract

In a semiconductor integrated circuit inspection method of inspecting a semiconductor integrated circuit including plural transistors according to which a test pattern generated for the semiconductor integrated circuit is input to an input terminal of the semiconductor integrated circuit, the time during which a voltage applied upon each of the transistors remains equal to or higher than a predetermined voltage is measured in response to inputting of the test pattern at the input terminal, and the ratio of thus measured time to the inspection time for the semiconductor integrated circuit is calculated. In certain example embodiments of this invention, this is advantageous in that it may be possible to verify whether a generated test pattern is preferable by grasping a state of voltage applied upon each transistor during a reliability test, so as to help maintain accuracy of reliability testing.

Claims

1. A semiconductor integrated circuit inspection method comprising the steps of:

inputting a test pattern, which is generated for a semiconductor integrated circuit comprising plural transistors, to said semiconductor integrated circuit;

measuring a time during which a voltage applied upon each of said transistors remains equal to or higher than a predetermined voltage, in response to inputting of said test pattern; and

calculating a ratio of the measured time to an inspection time for said semiconductor integrated circuit.

2. The semiconductor integrated circuit inspection method according to claim 1, wherein the time during which the voltage applied upon a gate of each of said transistors remains equal to or higher than the predetermined voltage is measured.

3. The semiconductor integrated circuit inspection method according to claim 1, wherein the time during which the voltage applied upon each of said transistors remains equal to or higher than the predetermined voltage is measured using a circuit simulator for said semiconductor integrated circuit.

4. The semiconductor integrated circuit inspection method according to claim 3, wherein said circuit simulator is a SPICE simulator and a connecting relation of said transistors is described in a SPICE net list.

5. The semiconductor integrated circuit inspection method according to claim 1, further comprising the steps of:

counting the number of transistors as for which calculated stress application time ratio to said inspection time is greater than a predetermined ratio; and

calculating the ratio of the count of the transistors to the total number of transistors which said semiconductor integrated circuit comprises.

6. The semiconductor integrated circuit inspection method according to claim 1, further comprising the steps of:

acquiring layout information regarding a location of each of said transistors; and

generating display data in which the locations according to said layout information regarding the location of each of said transistors are denoted at marks in plural colors depending upon the calculated ratio to said inspection time.

7. A semiconductor integrated circuit inspection apparatus for inspecting a semiconductor integrated circuit comprising plural transistors, in which a test pattern generated for said semiconductor integrated circuit is input to said semiconductor integrated circuit comprising:

a measuring part which measures a time during which a voltage applied upon each of said transistors remains equal to or higher than a predetermined voltage, in response to inputting of said test pattern; and

a calculating part which calculates a stress application time ratio of the measured time to an inspection time for said transistors of the measured time to an inspection time for said semiconductor integrated circuit.

8. The semiconductor integrated circuit inspection apparatus according to claim 7, wherein the time during which the voltage applied upon each of said transistors remains equal to or higher than the predetermined voltage is measured using a circuit simulator for said semiconductor integrated circuit.

9. The semiconductor integrated circuit inspection apparatus according to claim 8, wherein said circuit simulator is a SPICE simulator and a connecting relation of said transistors is described in a SPICE net list.