Post passivation method for semiconductor chip or wafer

• US 7,405,149 B1
• Filed: 05/24/2002
• Issued: 07/29/2008
• Est. Priority Date: 12/21/1998
• Status: Expired due to Fees

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Lee, Jin-Yuan, Lin, Mou-Shiung
• Primary Examiner(s): Ha; Nathan W
• Application Number:
  US10/154,662
• Time in Patent Office: 2,258 Days
• Field of Search: 438637-638, 438622-624, 438/626, 438/631, 438/633, 438/639, 438/118, 257758-759, 257/E21.499
• US Class Current: 438/622
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 21/76804 by forming tapered via holes
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/02311 Additive methods
• CPC Class Codes: H01L 2224/02313 Subtractive methods
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/1148 Permanent masks, i.e. masks left in the finished device, e.g. passivation layers
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/5222 Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5225 Shielding layers formed together with wiring layers
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/5228 Resistive arrangements or effects of, or between, wiring layers other resistive arrangements H01L23/647
• CPC Class Codes: H01L 23/525 with adaptable interconnections
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 23/5286 : Arrangements of power or ground buses
• CPC Class Codes: H01L 23/5329 : Insulating materials
• CPC Class Codes: H01L 23/53295 : Stacked insulating layers
• CPC Class Codes: H01L 23/60 : Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/12 : Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 27/0676 : comprising combinations of diodes, or capacitors or resistors
• CPC Class Codes: H01L 27/08 : including only semiconductor components of a single kind
• CPC Class Codes: H01L 28/10 : Inductors
• CPC Class Codes: H01L 28/20 : Resistors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01018 : Argon [Ar]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15174 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15184 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15192 : Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

The present invention adds one or more thick layers of polymer dielectric and one or more layers of thick, wide metal lines on top of a finished semiconductor wafer, post-passivation. The thick, wide metal lines may be used for long signal paths and can also be used for power buses or power planes, clock distribution networks, critical signal, and re-distribution of I/O pads for flip chip applications. Photoresist defined electroplating, sputter/etch, or dual and triple damascene techniques are used for forming the metal lines and via fill.

Claims

1. A method for fabricating an integrated circuit chip, comprising:

providing a silicon wafer, a transistor in or on said silicon wafer, a metallization structure over said silicon wafer, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer, a dielectric layer between said first and second metal layers, a contact pad over said silicon wafer, wherein said contact pad has a top surface and a sidewall, wherein said top surface has a first region and a second region between said first region and said sidewall, and a passivation layer over said metallization structure, over said dielectric layer and on said second region, wherein a first opening in said passivation layer is over said first region and exposes said first region, and wherein said passivation layer comprises a nitride;

forming a first polymer layer on said passivation layer, wherein a second opening in said first polymer layer is over said first region and exposes said first region, and wherein said first polymer layer has a thickness between 2 and 50 micrometers;

forming a third metal layer on said first polymer layer and on said contact pad, wherein said forming said third metal layer comprises sputtering a titanium-containing layer with a thickness between 0.01 and 3 micrometers on said first polymer layer and on said first region, sputtering a seed layer with a thickness between 0.05 and 3 micrometers on said titanium-containing layer, forming a photoresist layer on said seed layer, wherein a third opening in said photoresist layer is over said seed layer and exposes said seed layer, electroplating a gold layer with a thickness between 2 and 100 micrometers on said seed layer exposed by said third opening, removing said photoresist layer, removing said seed layer not under said gold layer, and removing said titanium-containing layer not under said gold layer; and

forming a second polymer layer on said third metal layer, on said first polymer layer, and over said silicon wafer, wherein a fourth opening in said second polymer layer is over said third metal layer and exposes said third metal layer.

2. The method of claim 1, wherein the position of said fourth opening from a top perspective view is different from that of said first opening.

3. The method of claim 1, after said forming said second polymer layer, further comprising forming a fourth metal layer connected to said third metal layer through said fourth opening.

4. The method of claim 3, wherein said forming said fourth metal layer comprises sputtering.

5. The method of claim 3, wherein said forming said fourth metal layer comprises electroplating.

6. The method of claim 1, wherein said first polymer layer comprises polyimide.

7. The method of claim 1, wherein said passivation layer further comprises an oxide.

8. The method of claim 1, wherein said nitride comprises oxynitride.

9. A method for fabricating an integrated circuit chip, comprising:

providing a silicon wafer, transistor in or on said silicon wafer, a metallization structure over said silicon wafer, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer, a dielectric layer between said first and second metal layers, a contact pad over said silicon wafer, and a passivation layer over said metallization structure and over said dielectric layer, wherein said passivation layer comprises a nitride;

forming a first polymer layer on said passivation layer, wherein a first opening in said first polymer layer is over said contact pad and exposes said contact pad, and wherein said first polymer layer has a thickness between 2 and 50 micrometers;

forming a third metal layer connected to said contact pad through said first opening, wherein said forming said third metal layer comprises sputtering a titanium-containing layer with a thickness between 0.01 and 3 micrometers, sputtering a seed layer with a thickness between 0.05 and 3 micrometers over said titanium-containing layer, forming a photoresist layer on said seed layer, wherein a second opening in said photoresist layer is over said seed layer and exposes said seed layer, electroplating a gold layer with a thickness between 2 and 100 micrometers on said seed layer exposed by said second opening, removing said photoresist layer, removing said seed layer not under said gold layer, and removing said titanium-containing layer not under said gold layer; and

forming a second polymer layer on said third metal layer and over said silicon wafer.

10. The method of claim 9, wherein a third opening in said second polymer layer is over said third metal layer and exposes said third metal layer, wherein the position of said third opening from a top perspective view is different from that of said first opening.

11. The method of claim 9, after said forming said second polymer layer, further comprising forming a fourth metal layer connected to said third metal layer through a third opening in said second polymer layer.

12. The method of claim 11, wherein said forming said fourth metal layer comprises sputtering.

13. The method of claim 11, wherein said forming said fourth metal layer comprises electroplating.

14. The method of claim 9, wherein said forming said third metal layer comprises said forming said third metal layer on said first polymer layer and on said contact pad.

15. The method of claim 9, wherein a third opening in said passivation layer is over said contact pad and exposes said contact pad.

16. The method of claim 9, wherein said first polymer layer comprises polyimide.

17. The method of claim 9, wherein said passivation layer further comprises an oxide.

18. The method of claim 9, wherein said nitride comprises oxynitride.

19. A method for fabricating an integrated circuit chip, comprising:

providing a silicon wafer, a transistor in or on said silicon wafer, a metallization structure over said silicon wafer, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer, a dielectric layer between said first and second metal layers, a contact pad over said silicon wafer, and a passivation layer over said metallization structure and over said dielectric layer, wherein a first opening in said passivation layer is over said contact pad and exposes said contact pad, and wherein said passivation layer comprises a nitride;

forming a third metal layer over said passivation layer and over said contact pad, wherein said third metal layer is connected to said contact pad through said first opening, wherein said forming said third metal layer comprises sputtering an adhesion layer with a thickness between 0.01 and 3 micrometers, sputtering a seed layer with a thickness between 0.05 and 3 micrometers over said adhesion layer, forming a photoresist layer on said seed layer, wherein a second opening in said photoresist layer is over said seed layer and exposes said seed layer, electroplating a gold layer with a thickness between 2 and 100 micrometers on said seed layer exposed by said second opening, removing said photoresist layer, removing said seed layer not under said gold layer, and removing said adhesion layer not under said gold layer; and

forming a first polymer layer on said third metal layer, over said passivation layer, and over said silicon wafer.

20. The method of claim 19, wherein a third opening in said first polymer layer is over said third metal layer and exposes said third metal layer.

21. The method of claim 20, wherein the position of said third opening from a top perspective view is different from that of said first opening.

22. The method of claim 20, after said forming said first polymer layer, further comprising forming a fourth metal layer connected to said third metal layer through said third opening.

23. The method of claim 22, wherein said forming said fourth metal layer comprises sputtering.

24. The method of claim 22, wherein said forming said fourth metal layer comprises electroplating.

25. The method of claim 19 further comprising forming a second polymer layer on said passivation layer, wherein a third opening in said second polymer layer is over said contact pad and exposes said contact pad, followed by said forming said third metal layer further on said second polymer layer.

26. The method of claim 25, wherein said second polymer layer has a thickness between 2 and 50 micrometers.

27. The method of claim 19, wherein said nitride comprises silicon nitride.

28. The method of claim 19, wherein said nitride comprises silicon oxynitride.

29. The method of claim 25, wherein said second polymer layer comprises polyimide.

30. The method of claim 19, wherein said passivation layer further comprises an oxide.

31. The method of claim 19, wherein said nitride comprises oxynitride.