Post passivation interconnection schemes on top of the IC chips

• US 7,405,150 B2
• Filed: 11/14/2005
• Issued: 07/29/2008
• Est. Priority Date: 10/18/2000
• Status: Expired due to Term

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Lee, Jin-Yuan, Lin, Mou-Shiung
• Primary Examiner(s): Ghyka; Alexander G
• Application Number:
  US11/273,071
• Publication Number:
  US 20060068574A1
• Time in Patent Office: 988 Days
• Field of Search: 438/618, 438/622, 438/127
• US Class Current: 438/622
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 21/76801 characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 23/5222 Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 23/60 Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 23/62 Protection against overvoltage, e.g. fuses, shunts
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2924/12044 OLED
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.

Claims

1. A method for fabricating an IC chip comprising:

providing a silicon substrate, a first internal circuit in or on said silicon substrate, a second internal circuit in or on said silicon substrate, a dielectric layer over said silicon substrate, a first interconnecting structure over said silicon substrate and in said dielectric layer, wherein said first interconnecting structure is connected to said first internal circuit, a second interconnecting structure over said silicon substrate and in said dielectric layer, wherein said second interconnecting structure is connected to said second internal circuit, and wherein said first and second interconnecting structures are formed by a damascene process comprising a dielectric etching process, an electroplating process and a CMP process, wherein said electroplating process is followed by said CMP process, and a passivation layer over said dielectric layer, wherein said passivation layer comprises a nitride layer; and

forming a polymer layer and a third interconnecting structure over said passivation layer, wherein said third interconnecting structure is in said polymer layer, wherein said third interconnecting structure is connected to said first and second interconnecting structures, wherein said first internal circuit is connected to said second internal circuit through, in sequence, said first interconnecting structure, said third interconnecting structure and said second interconnecting structure, and wherein said third interconnecting structure is formed by a process comprising sputtering a thin base metal layer, followed by forming a patterned photoresist layer, followed by electroplating a thick metal layer, followed by removing said patterned photoresist layer, followed by etching said thin base metal layer.

2. The method of claim 1, wherein said third interconnecting structure comprises a power bus connecting said first interconnecting structure to said second interconnecting structure.

3. The method of claim 1, wherein said third interconnecting structure comprises a ground bus connecting said first interconnecting structure to said second interconnecting structure.

4. The method of claim 1 further comprising providing an ESD circuit in or on said silicon substrate, and a fourth interconnecting structure over said silicon substrate and in said dielectric layer, wherein said fourth interconnecting structure is connected to said ESD circuit, wherein said ESD circuit is connected to said first internal circuit through, in sequence, said fourth interconnecting structure, said third interconnecting structure and said first interconnecting structure, and wherein said ESD circuit is connected to said second internal circuit through, in sequence, said fourth interconnecting structure, said third interconnecting structure and said second interconnecting structure.

5. The method of claim 1 further comprising providing a driver, receiver or I/O circuit in or on said silicon substrate, a fourth interconnecting structure over said silicon substrate and in said dielectric layer, wherein said fourth interconnecting structure is connected to a first terminal of said driver, receiver or I/O circuit, a fifth interconnecting structure over said silicon substrate and in said dielectric layer, wherein said fifth interconnecting structure is connected to a second terminal of said driver, receiver or I/O circuit, and an external connection connected to said second terminal through said fifth interconnecting structure, wherein said first terminal is connected to said first internal circuit through, in sequence, said fourth interconnecting structure, said third interconnecting structure and said first interconnecting structure, and wherein said first terminal is connected to said second internal circuit through, in sequence, said fourth interconnecting structure, said third interconnecting structure and said second interconnecting structure.

6. The method of claim 5 further comprising an ESD circuit in or on said silicon substrate, wherein said second terminal is connected to said ESD circuit through said fifth interconnecting structure.

7. The method of claim 1 further comprising providing a third internal circuit in or on said silicon substrate, wherein said third internal circuit is connected to said first internal circuit through said first interconnecting structure, and wherein said third internal circuit is connected to said second internal circuit through, in sequence, said first interconnecting structure, said third interconnecting structure and said second interconnecting structure.

8. The method of claim 7 further comprising providing a fourth internal circuit in or on said silicon substrate, wherein said fourth internal circuit is connected to said second internal circuit through said second interconnecting structure, and wherein said first and third internal circuits are connected to said fourth internal circuit through, in sequence, said first interconnecting structure, said third interconnecting structure and said second interconnecting structure.

9. The method of claim 1, wherein said third interconnecting structure comprises an interconnect line having a thickness greater than 1 micrometer.

10. The method of claim 1, wherein said third interconnecting structure comprises a signal line connecting said first interconnecting structure to said second interconnecting structure.

11. The method of claim 1, wherein said third interconnecting structure comprises a clock line connecting said first interconnecting structure to said second interconnecting structure.

12. A method for fabricating an IC chip comprising:

providing a silicon substrate, an ESD circuit in or on said silicon substrate, a first internal circuit in or on said silicon substrate, a dielectric layer over said silicon substrate, a first interconnecting structure over said silicon substrate and in said dielectric layer, wherein said first interconnecting structure is connected to said ESD circuit, a second interconnecting structure over said silicon substrate and in said dielectric layer, wherein said second interconnecting structure is connected to said first internal circuit, and wherein said first and second interconnecting structures are formed by a damascene process comprising a dielectric etching process, an electroplating process and a CMP process, wherein said electroplating process is followed by said CMP process, and a passivation layer over said dielectric layer, wherein said passivation layer comprises a nitride layer; and

forming a polymer layer and a third interconnecting structure over said passivation layer, wherein said third interconnecting structure is in said polymer layer, wherein said third interconnecting structure is connected to said first and second interconnecting structures, wherein said ESD circuit is connected to said first internal circuit through, in sequence, said first interconnecting structure, said third interconnecting structure and said second interconnecting structure, and wherein said third interconnecting structure is formed by a process comprising sputtering a thin base metal layer, followed by forming a patterned photoresist layer, followed by electroplating a thick metal layer, followed by removing said patterned photoresist layer, followed by etching said thin base metal layer.

13. The method of claim 12, wherein said third interconnecting structure comprises a power bus connecting said first interconnecting structure to said second interconnecting structure.

14. The method of claim 12, wherein said third interconnecting structure comprises a ground bus connecting said first interconnecting structure to said second interconnecting structure.

15. The method of claim 12 further comprising providing a second internal circuit in or on said silicon substrate, and a fourth interconnecting structure over said silicon substrate and in said dielectric layer, wherein said fourth interconnecting structure is connected to said second internal circuit and to said third interconnecting structure, wherein said ESD circuit is connected to said second internal circuit through, in sequence, said first interconnecting structure, said third interconnecting structure and said fourth interconnecting structure, and wherein said first internal circuit is connected to said second internal circuit through, in sequence, said second interconnecting structure, said third interconnecting structure and said fourth interconnecting structure.

16. The method of claim 15 further comprising providing a third internal circuit in or on said silicon substrate, wherein said second interconnecting structure is connected to said third internal circuit, wherein said first internal circuit is connected to said third internal circuit through said second interconnecting structure, wherein said ESD circuit is connected to said third internal circuit through, in sequence, said first interconnecting structure, said third interconnecting structure and said second interconnecting structure, and wherein said third internal circuit is connected to said second internal circuit through, in sequence, said second interconnecting structure, said third interconnecting structure and said fourth interconnecting structure.

17. The method of claim 16 further comprising providing a fourth internal circuit in or on said silicon substrate, wherein said fourth interconnecting structure is connected to said fourth internal circuit, wherein said second internal circuit is connected to said fourth internal circuit through said fourth interconnecting structure, wherein said ESD circuit is connected to said fourth internal circuit through, in sequence, said first interconnecting structure, said third interconnecting structure and said fourth interconnecting structure, and wherein said first and third internal circuits are connected to said fourth internal circuit through, in sequence, said second interconnecting structure, said third interconnecting structure and said fourth interconnecting structure.

18. The method of claim 12 further comprising providing a second internal circuit in or on said silicon substrate, wherein said second interconnecting structure is connected to said second internal circuit, wherein said first internal circuit is connected to said second internal circuit through said second interconnecting structure, and wherein said ESD circuit is connected to said second internal circuit through, in sequence, said first interconnecting structure, said third interconnecting structure and said second interconnecting structure.

19. The method of claim 12, wherein said third interconnecting structure comprises an interconnect line having a thickness greater than 1 micrometer.

20. The method of claim 12, wherein said polymer layer has a thickness greater than 2 micrometers.

21. A method for fabricating an IC chip comprising:

providing a silicon substrate, a driver, receiver or I/O circuit in or on said silicon substrate, a first internal circuit in or on said silicon substrate, a dielectric layer over said silicon substrate, a first interconnecting structure over said silicon substrate and in said dielectric layer, wherein said first interconnecting structure is connected to a first terminal of said driver, receiver or I/O circuit, a second interconnecting structure over said silicon substrate and in said dielectric layer, wherein said second interconnecting structure is connected to said first internal circuit, and wherein said first and second interconnecting structures are formed by a damascene process comprising a dielectric etching process, an electroplating process and a CMP process, wherein said electroplating process is followed by said CMP process, and a passivation layer over said dielectric layer, wherein said passivation layer comprises a nitride layer; and

forming a polymer layer and a third interconnecting structure over said passivation layer, wherein said third interconnecting structure is in said polymer layer, wherein said third interconnecting structure is connected to said first and second interconnecting structures, wherein said first terminal is connected to said first internal circuit through, in sequence, said first interconnecting structure, said third interconnecting structure and said second interconnecting structure, and wherein said third interconnecting structure is formed by a process comprising sputtering a thin base metal layer, followed by forming a patterned photoresist layer, followed by electroplating a thick metal layer, followed by removing said patterned photoresist layer, followed by etching said thin base metal layer.

22. The method of claim 21 further comprising providing an ESD circuit in or on said silicon substrate, a fourth interconnecting structure over said silicon substrate and in said dielectric layer, wherein said ESD circuit is connected to a second terminal of said driver, receiver or I/O circuit through said fourth interconnecting structure, and an external connection connected to said second terminal and to said ESD circuit through said fourth interconnecting structure.

23. The method of claim 21 further comprising providing a second internal circuit in or on said silicon substrate, and a fourth interconnecting structure over said silicon substrate and in said dielectric layer, wherein said fourth interconnecting structure is connected to said second internal circuit and to said third interconnecting structure, wherein said first terminal is connected to said second internal circuit through, in sequence, said first interconnecting structure, said third interconnecting structure and said fourth interconnecting structure, and wherein said first internal circuit is connected to said second internal circuit through, in sequence, said second interconnecting structure, said third interconnecting structure and said fourth interconnecting structure.

24. The method of claim 23 further comprising providing a third internal circuit in or on said silicon substrate, wherein said second interconnecting structure is connected to said third internal circuit, wherein said first internal circuit is connected to said third internal circuit through said second interconnecting structure, wherein said first terminal is connected to said third internal circuit through, in sequence, said first interconnecting structure, said third interconnecting structure and said second interconnecting structure, and wherein said third internal circuit is connected to said second internal circuit through, in sequence, said second interconnecting structure, said third interconnecting structure and said fourth interconnecting structure.

25. The method of claim 21, wherein said third interconnecting structure comprises a signal line connecting said first interconnecting structure to said second interconnecting structure.

26. The method of claim 21, wherein said third interconnecting structure comprises an interconnect line having a thickness greater than 1 micrometer.

27. The method of claim 21, wherein said third interconnecting structure comprises a clock line connecting said first interconnecting structure to said second interconnecting structure.

28. The method of claim 21, wherein said polymer layer has a thickness greater than 2 micrometers.

29. A method for fabricating an IC chip comprising:

providing a silicon substrate, a first metallization structure over said silicon substrate, wherein said first metallization structure comprises a first metal layer over said silicon substrate, a second metal layer over said silicon substrate and over said first metal layer, a first metal interconnect over said silicon substrate, a second metal interconnect over said silicon substrate, and a third metal interconnect over said silicon substrate and between said first and second metal interconnects, wherein said first, second and third metal interconnects are separated from one another by an insulating material, and wherein said first metallization structure is formed by a damascene process comprising a dielectric etching process, an electroplating process and a CMP process, wherein said electroplating process is followed by said CMP process, a dielectric layer between said first and second metal layers, a passivation layer over said first metallization structure, over said dielectric layer and on said third metal interconnect, wherein said passivation layer comprises a nitride layer, and wherein said first, second and third metal interconnects are provided by a topmost metal layer under said passivation layer, and a first polymer layer on said passivation layer and over said third metal interconnect, wherein said first polymer layer has a thickness between 2 and 150 micrometers, and wherein a first opening in said first polymer layer and in said passivation layer is over a first contact point of said first metal interconnect and exposes said first contact point, and a second opening in said first polymer layer and in said passivation layer is over a second contact point of said second metal interconnect and exposes said second contact point; and

forming a second metallization structure on said first polymer layer, over said passivation layer, over said first and second contact points and over said third metal interconnect, wherein said third metal interconnect is directly under said second metallization structure and is not connected to said second metallization structure through any opening in said first polymer layer under said second metallization structure, wherein said first contact point is connected to said second contact point through said second metallization structure, and wherein said second metallization structure is formed by a process comprising sputtering a thin base metal layer, followed by forming a patterned photoresist layer, followed by electroplating a thick metal layer, followed by removing said patterned photoresist layer, followed by etching said thin base metal layer.

30. The method of claim 29, wherein said first polymer layer comprises polyimide.

31. The method of claim 29, wherein said first polymer layer comprises benzocyclobutene (BCB).

32. The method of claim 29 further comprising forming a second polymer layer on said second metallization structure.

33. The method of claim 32, wherein said second polymer layer comprises polyimide.

34. The method of claim 29, wherein said passivation layer further comprises an oxide layer.

35. The method of claim 29, wherein said first opening has a transverse dimension between 0.5 and 30 micrometers.

36. The method of claim 35, wherein said second opening has a transverse dimension between 0.5 and 30 micrometers.

37. The method of claim 29, wherein said second metallization structure comprises an interconnecting line with a thickness greater than 1 micrometer.