Capacitor constructions and semiconductor structures

• US 7,405,438 B2
• Filed: 09/20/2004
• Issued: 07/29/2008
• Est. Priority Date: 04/25/2003
• Status: Expired due to Fees

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Ping, Er-Xuan, Breiner, Lyle D., Doan, Trung Tri, Blalock, Guy T., Chen, Shenlin
• Primary Examiner(s): WOJCIECHOWICZ, EDWARD JOSEPH
• Application Number:
  US10/945,774
• Publication Number:
  US 20050042824A1
• Time in Patent Office: 1,408 Days
• Field of Search: 257/296, 257/301, 257/303, 257/306, 257/309, 257/532
• US Class Current: 257/306
• CPC Class Codes: H01L 28/84 being a rough surface, e.g. using hemispherical grains
• CPC Class Codes: H10B 12/033 the capacitor extending over the transistor
• CPC Class Codes: H10B 12/318 the storage electrode having multiple segments
• CPC Class Codes: Y10S 438/964 Roughened surface

Abstract

The invention includes a method of forming a rugged semiconductor-containing surface. A first semiconductor layer is formed over a substrate, and a second semiconductor layer is formed over the first semiconductor layer. Subsequently, a third semiconductor layer is formed over the second semiconductor layer, and semiconductor-containing seeds are formed over the third semiconductor layer. The seeds are annealed to form the rugged semiconductor-containing surface. The first, second and third semiconductor layers are part of a common stack, and can be together utilized within a storage node of a capacitor construction. The invention also includes semiconductor structures comprising rugged surfaces. The rugged surfaces can be, for example, rugged silicon.

Claims

1. A capacitor construction, comprising:

a first capacitor electrode, the first capacitor electrode including a stack comprising at least three semiconductor layers, two of the three semiconductor layers being adjacent one another;

a bottom of the stack being conductively-doped semiconductor material and an outer surface of the stack being a rugged semiconductor surface, there being an interface layer in the stack, the interface layer being between the adjacent semiconductor layers;

wherein the conductively-doped semiconductor material of the bottom of the stack does not directly contact the rugged semiconductor outer surface of the stack;

at least one dielectric material over the first capacitor electrode; and

a second capacitor electrode over the at least one dielectric material.

2. The capacitor construction of claim 1 wherein the rugged semiconductor surface comprises silicon.

3. The capacitor construction of claim 1 wherein the interface layer has a thickness of less than or equal to about 10 Å

.

4. The capacitor construction of claim 1 wherein the interface layer comprises silicon dioxide.

5. A capacitor construction, comprising:

a first capacitor electrode, the first capacitor electrode including a stack comprising at least three semiconductor layers, two of the three semiconductor layers being adjacent one another;

a bottom of the stack being conductively-doped semiconductor material and an outer surface of the stack being a rugged semiconductor surface, there being an interface layer in the stack, the interface layer being between the adjacent semiconductor layers;

the conductively-doped semiconductor material of the bottom of the stack not being in direct contact with the rugged semiconductor surface;

at least one dielectric material over the first capacitor electrode;

a second capacitor electrode over the at least one dielectric material; and

wherein the interface layer comprises silicon nitride.

6. A capacitor construction, comprising:

a first capacitor electrode, the first capacitor electrode including a stack comprising at least three semiconductor layers, two of the three semiconductor layers being adjacent one another;

a bottom of the stack being conductively-doped semiconductor material and an outer surface of the stack being a rugged semiconductor surface, there being an interface layer in the stack, the interface layer being between the adjacent semiconductor layers;

the conductively-doped semiconductor material of the bottom of the stack not being in direct contact with the rugged semiconductor surface;

at least one dielectric material over the first capacitor electrode;

a second capacitor electrode over the at least one dielectric material; and

wherein the adjacent semiconductor layers consist of silicon or doped silicon, and the interface layer comprises Si/Ge.