Semiconductor device containing dielectrically isolated PN junction for enhanced breakdown characteristics

• US 7,405,452 B2
• Filed: 02/02/2004
• Issued: 07/29/2008
• Est. Priority Date: 02/02/2004
• Status: Expired due to Fees

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Hamza Yilmaz
• Inventors: Yilmaz, Hamza
• Primary Examiner(s): Pert; Evan
• Assistant Examiner(s): MANDALA, VICTOR A
• Application Number:
  US10/771,593
• Publication Number:
  US 20050167695A1
• Time in Patent Office: 1,639 Days
• Field of Search: 257/134, 257/135, 257328-332, 257/409, 257/471, 257/E29.31, 257E29311-E29313
• US Class Current: 257/409
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/808 with a PN junction gate , e.g. PN homojunction gate H01L29/7725, H01L29/775, H01L29/778, H01L29/806 take precedence
• CPC Class Codes: H01L 29/8083 Vertical transistors SIT H01L29/7722
• CPC Class Codes: H01L 29/8605 Resistors with PN junctions
• CPC Class Codes: H01L 29/872 : Schottky diodes

Abstract

A semiconductor device includes a field shield region that is doped opposite to the conductivity of the substrate and is bounded laterally by dielectric sidewall spacers and from below by a PN junction. For example, in a trench-gated MOSFET the field shield region may be located beneath the trench and may be electrically connected to the source region. When the MOSFET is reverse-biased, depletion regions extend from the dielectric sidewall spacers into the “drift” region, shielding the gate oxide from high electric fields and increasing the avalanche breakdown voltage of the device. This permits the drift region to be more heavily doped and reduces the on-resistance of the device. It also allows the use of a thin, 20 Å gate oxide for a power MOSFET that is to be switched with a 1V signal applied to its gate while being able to block over 30V applied across its drain and source electrodes, for example.

Claims

1. A semiconductor device comprising:

a semiconductor substrate comprising;

a region of a first conductivity type; and

a field shield region of a second conductivity type, said field shield region being laterally bounded by dielectric sidewalls, said dielectric sidewalls laterally separating said field shield region from said region of the first conductivity type, said field shield region being bounded from below by a PN junction with said region of the first conductivity type;

a top electrode in electrical contact with a top surface of said substrate;

a bottom electrode in electrical contact with a bottom surface of said substrate; and

a shield electrode in electrical contact with the field shield region,

wherein the electrical contact between the shield electrode and the field shield region is ohmic.

2. A semiconductor device comprising:

a semiconductor substrate comprising;

a region of a first conductivity type; and

a field shield region of a second conductivity type, said field shield region being laterally bounded by dielectric sidewalls, said dielectric sidewalls separating said field shield region from said region of the first conductivity type, said field shield region being bounded from below by a PN junction with said region of the first conductivity type;

a top electrode in electrical contact with a top surface of said substrate;

a bottom electrode in electrical contact with a bottom surface of said substrate; and

a shield electrode in electrical contact with the field shield region,

wherein the electrical contact between the top electrode and the top surface is ohmic.

3. A semiconductor device comprising:

a semiconductor substrate comprising;

a region of a first conductivity type; and

a field shield region of a second conductivity type, said field shield region being laterally bounded by dielectric sidewalls, said dielectric sidewalls separating said field shield region from said region of the first conductivity type, said field shield region being bounded from below by a PN junction with said region of the first conductivity type;

a top electrode in electrical contact with a top surface of said substrate;

a bottom electrode in electrical contact with a bottom surface of said substrate; and

a shield electrode in electrical contact with the field shield region,

wherein the electrical contact between the bottom electrode and the bottom surface is ohmic.

4. A semiconductor device comprising:

a semiconductor substrate comprising a vertical JFET, said vertical JFET comprising;

a region of a first conductivity type; and

a field shield region of a second conductivity type, said field shield region being laterally bounded by dielectric sidewalls, said dielectric sidewalls separating said field shield region from said region of the first conductivity type, said field shield region being bounded from below by a PN junction with said region of the first conductivity type;

a top electrode in ohmic electrical contact with a top surface of said substrate;

a bottom electrode in ohmic electrical contact with a bottom surface of said substrate; and

a shield electrode in electrical contact with the field shield region.

5. A semiconductor device comprising:

a semiconductor substrate comprising;

a region of a first conductivity type; and

a field shield region of a second conductivity type, said field shield region being laterally bounded by dielectric sidewalls, said dielectric sidewalls separating said field shield region from said region of the first conductivity type, said field shield region being bounded from below by a PN junction with said region of the first conductivity type;

a top electrode in electrical contact with a top surface of said substrate;

a bottom electrode in electrical contact with a bottom surface of said substrate; and

a shield electrode in electrical contact with the field shield region,

wherein the contact between the top electrode and the top surface of said substrate is a Schottky barrier contact and the contact between the bottom electrode and the bottom surface of said substrate is ohmic.