Electronic apparatus with deposited dielectric layers

• US 7,405,454 B2
• Filed: 08/26/2005
• Issued: 07/29/2008
• Est. Priority Date: 03/04/2003
• Status: Expired due to Fees

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Ahn, Kie Y., Forbes, Leonard
• Primary Examiner(s): Menz; Douglas M.
• Application Number:
  US11/213,013
• Publication Number:
  US 20060001151A1
• Time in Patent Office: 1,068 Days
• Field of Search: 257/410, 257/411, 257/506
• US Class Current: 257/410
• CPC Class Codes: H01L 21/02175 characterised by the metal H01L21/02197 takes precedence
• CPC Class Codes: H01L 21/02181 the material containing hafnium, e.g. HfO2
• CPC Class Codes: H01L 21/0228 deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
• CPC Class Codes: H01L 21/28229 by deposition of a layer, e.g. metal, metal compound or poysilicon, followed by transformation thereof into an insulating layer
• CPC Class Codes: H01L 21/3141 Deposition using atomic layer deposition techniques [ALD]
• CPC Class Codes: H01L 21/31645 Deposition of Hafnium oxides, e.g. HfO2
• CPC Class Codes: H01L 21/31683 of metallic layers, e.g. Al deposited on the body, e.g. formation of multi-layer insulating structures
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 12/05 Making the transistor

Abstract

An atomic layer deposited dielectric layer and a method of fabricating such a dielectric layer produce a reliable dielectric layer having an equivalent oxide thickness thinner than attainable using SiO₂. Depositing a hafnium metal layer on a substrate surface by atomic layer deposition and depositing a hafnium oxide layer on the hafnium metal layer by atomic layer deposition form a hafnium oxide dielectric layer substantially free of silicon oxide. Dielectric layers containing atomic layer deposited hafnium oxide are thermodynamically stable such that the hafnium oxide will have minimal reactions with a silicon substrate or other structures during processing.

Claims

1. An electronic device comprising:

a silicon substrate;

a dielectric layer disposed on the silicon substrate;

the dielectric layer having a dielectric film structured as one or more monolayers of a metal oxide, the dielectric film having a surface with a roughness less than or equal to a micro-roughness due to partial monolayer formation of the dielectric film, the dielectric layer having an interfacial layer, the interfacial layer in contact with the silicon substrate essentially without a SiO_x layer contacting the silicon substrate.

2. The electronic device of claim 1, wherein the dielectric layer includes an amorphous hafnium oxide layer.

3. The electronic device of claim 1, wherein the dielectric layer includes a hafnium oxide layer substantially free of silicon oxide.

4. The electronic device of claim 1, wherein the electronic device includes a hafnium silicide layer as the interfacial layer.

5. The electronic device of claim 1, wherein the dielectric layer has an equivalent oxide thickness less than or equal to 12 Å

.

6. The electronic device of claim 1, wherein the dielectric layer is a capacitor dielectric of a capacitor.

7. The electronic device of claim 1, wherein the dielectric layer is a gate dielectric of a transistor.

8. The electronic device of claim 1, wherein the dielectric layer is a dielectric layer in a memory.

9. The electronic device of claim 1, wherein the electronic device includes conductive paths to a conductive layer contacting the dielectric layer to provide a signal to the conductive layer from devices in an electronic system.

10. A capacitor, comprising:

a first conductive layer on a silicon substrate;

a dielectric layer disposed on the first conductive layer, the dielectric layer disposed on the silicon substrate, the dielectric layer having a dielectric film structured as one or more monolayers of a metal oxide, the dielectric film having a surface with a roughness less than or equal to a micro-roughness due to partial monolayer formation of the dielectric film, the dielectric layer having an interfacial layer, the interfacial layer contacting the first conductive layer essentially without a SiO_x layer contacting the first conductive layer; and

a second conductive layer disposed on the dielectric layer.

11. The capacitor of claim 10, wherein the metal oxide includes hafnium.

12. The capacitor of claim 11, wherein the interfacial layer is structured by forming a layer of hafnium on the first conductive layer by atomic layer deposition including performing a number of cycles ranging from 4 to 10 cycles to deposit the layer of hafnium on the substrate and forming hafnium oxide on the layer of hafnium to substantially convert the layer of hafnium to hafnium oxide.

13. The capacitor of claim 10, wherein the dielectric layer has a dielectric constant in the range from about 8 to about 25.

14. A transistor comprising:

a silicon body region between a source region and a drain region on a silicon substrate;

a dielectric layer disposed on the silicon body region between the source region and the drain region, the dielectric layer having a dielectric film structured as one or more monolayers of a metal oxide, the dielectric film having a surface with a roughness less than or equal to a micro-roughness due to partial monolayer formation of the dielectric film, the dielectric layer having an interfacial layer, the interfacial layer contacting the silicon body region essentially without a SiO_x layer contacting the silicon body region; and

a gate coupled to the dielectric layer.

15. The transistor of claim 14, wherein the metal oxide includes hafnium.

16. The transistor of claim 15, wherein the interfacial layer is structured by forming a layer of hafnium on the body region by atomic layer deposition including performing a number of cycles ranging from 4 to 10 cycles to deposit the layer of hafnium on the body region and forming hafnium oxide on the layer of hafnium to substantially convert the layer of hafnium to hafnium oxide.

17. The transistor of claim 15, wherein the dielectric layer has a dielectric constant in the range from about 8 to about 25.

18. The transistor of claim 15, wherein the dielectric layer has an equivalent oxide thickness (t_eq) equal to or less than 10 Angstroms.

19. A memory comprising:

a number of access transistors, at least one access transistor including a gate coupled to a dielectric layer, the dielectric layer disposed on a silicon body region between a source region and a drain region on a silicon substrate, the dielectric layer having a dielectric film structured as one or more monolayers of a metal oxide, the dielectric film having a surface with a roughness less than or equal to a micro-roughness due to partial monolayer formation of the dielectric film, the dielectric layer having an interfacial layer, the interfacial layer contacting the silicon body region essentially without a SiO_x layer contacting the body region;

a number of word lines coupled to the number of access transistors; and

a number of bit lines coupled to the number of access transistors.

20. The memory of claim 19, wherein the metal oxide includes hafnium.

21. The memory of claim 20, wherein the interfacial layer is structured by forming a layer of hafnium on the body region by atomic layer deposition including performing a number of cycles ranging from 4 to 10 cycles to deposit the layer of hafnium on the body region and forming hafnium oxide on the layer of hafnium to substantially convert the layer of hafnium to hafnium oxide.

22. The memory of claim 20, wherein the dielectric layer has a dielectric constant in the range from about 8 to about 25.

23. The memory of claim 20, wherein the dielectric layer has an equivalent oxide thickness (teq) equal to or less than 12 Angstroms.

24. An electronic system comprising:

a processor;

a system bus; and

a memory coupled to the processor by the system bus, the memory including;

a number of access transistors, at least one access transistor including a gate coupled to a dielectric layer, the dielectric layer disposed on a silicon body region between a source region and a drain region on a silicon substrate, the dielectric layer having a dielectric film structured as one or more monolayers of a metal oxide, the dielectric film having a surface with a roughness less than or equal to a micro-roughness due to partial monolayer formation of the dielectric film, the dielectric layer having an interfacial layer, the interfacial layer contacting the silicon body region essentially without a SiO_x layer contacting the silicon body region;

a number of word lines coupled to the number of access transistors; and

a number of bit lines coupled to the number of access transistors.

25. The electronic system of claim 24, wherein the metal oxide includes hafnium.

26. The electronic system of claim 25, wherein the interfacial layer is structured by forming a layer of hafnium on the body region by atomic layer deposition including performing a number of cycles ranging from 4 to 10 cycles to deposit the layer of hafnium on the body region and forming hafnium oxide on the layer of hafnium to substantially convert the layer of hafnium to hafnium oxide.

27. The electronic system of claim 25, wherein the dielectric layer has a dielectric constant in the range from about 8 to about 25.

28. The electronic system of claim 25, wherein the dielectric layer has an equivalent oxide thickness (t_eq) equal to or less than 12 Angstroms.